Processor state aware interrupts from peripherals
View Patent ↗A method, apparatus and computer product wherein interrupt thresholds are automatically adjusted based on the current state of the processor. The processor provides an output signal, possibly on one or more lines, that is indicative of the state the processor is in such as active, idle sleep. The peripherals monitor this signal and their interrupt thresholds are varied to be low when the processor is active and to be high when the processor is asleep. This causes the peripherals to delay their respective interrupts when the processor is asleep. When the processor is awakened, all peripherals requiring it may be serviced.
1. In a computer system having a processor with a plurality of activity states, and a plurality of peripheral devices in operative relation with the processor, wherein each peripheral device has a plurality of urgency states, a method of operating the computer system comprising:
communicating an activity state of the processor to the peripheral devices;
evaluating an activity state of the processor against an urgency state of a peripheral device to determine whether said peripheral device issues an interrupt, wherein if said urgency state of a peripheral device is high, said peripheral device issues an interrupt to said processor regardless of said activity state of said processor;
issuing interrupt requests to said processor from all peripheral devices which need to be serviced, when an interrupt has been issued to said processor by one of said peripheral devices; and
servicing all of said interrupt requests by said processor.
2. A method as recited in claim 1 , further comprising:
supplying an interrupt from the peripheral devices to the processor when the processor changes activity states from a first activity state to a second activity state.
3. A method as recited in claim 2 , further comprising detection of the activity state of the processor by the peripheral devices before said interrupt is supplied.
4. A method as recited in claim 2 , wherein the peripheral devices have a plurality of urgency states and an activity state of the processor is evaluated against an urgency state of a peripheral device to determine whether said peripheral device issues an interrupt.
5. A method as recited in claim 4 , wherein if said urgency state of a peripheral device is low, said peripheral device issues an interrupt to said processor only if said activity state of said processor is other than low.
6. A method as recited in claim 1 , further comprising setting the urgency level of each of the peripherals that have been serviced to a lowest urgency level after the peripheral has been serviced.
7. A method as recited in claim 1 , wherein the activity states of the processor are represented by at least one bit output of the processor.
8. A method as recited in claim 1 , wherein the activity states of the processor are represented by at least one output word generated by the processor.
9. A method as recited in claim 1 , wherein the activity state of the processor is communicated as being in a state selected from active, idle and sleep.
10. A computer system having a processor with a plurality of activity states, and a plurality of peripheral devices in operative relation with the processor, wherein each peripheral device has a plurality of urgency states, the computer system comprising:
means for communicating an activity state of the processor to the peripheral devices;
means for evaluating an activity state of the processor against an urgency state of a peripheral device to determine whether said peripheral device issues an interrupt, wherein if said urgency state of a peripheral device is high, said peripheral device issues an interrupt to said processor regardless of said activity state of said processor; and
means associated with each of said peripheral devices for detecting when an interrupt has been issued to said processor by one of said peripheral devices, and for issuing an interrupt request to said processor if said peripheral device needs to be serviced;
wherein said processor servicing all of said interrupt requests from peripheral devices needing to be serviced.
11. A system as recited in claim 10 , further comprising means for supplying an interrupt from the peripheral devices to the processor when the processor changes activity states from a first activity state to a second activity state.
12. A system as recited in claim 11 , further comprising detection means associated with the peripheral devices for detecting the activity state of the processor before said interrupt is supplied.
13. A system as recited in claim 11 , wherein the peripheral devices have a plurality of urgency states, further comprising means for evaluating an activity state of the processor against an urgency state of a peripheral device to determine whether said peripheral device issues an interrupt.
14. A system as recited in claim 13 , wherein if said urgency state of a peripheral device is low, said peripheral device issues an interrupt to said processor only if said activity state of said processor is other than low.
15. A system as recited in claim 10 , further comprising:
means for setting the urgency level of each of the peripherals that have been serviced to a lowest urgency level after the peripheral has been serviced.
16. A system as recited in claim 1 , wherein the activity states of the processor are represented by at least one bit output of the processor.
17. A system as recited in claim 1 , wherein the activity states of the processor are represented by at least one output word generated by the processor.
18. A system as recited in claim 1 , wherein the processor has activity states selected from active, idle and sleep.
19. A computer program product comprising a computer usable medium having computer readable program code means embodied therein for causing the computer to effect a method for operating the computer system to service interrupts from a plurality of peripheral devices in operative relation with a processor having a plurality of activity states, the method comprising:
communicating an activity state of the processor to the peripheral devices;
evaluating an activity state of the processor against an urgency state of a peripheral device to determine whether said peripheral device issues an interrupt, wherein if said urgency state of a peripheral device is high, said peripheral device issues an interrupt to said processor regardless of said activity state of said processor;
issuing interrupt requests to said processor from all peripheral devices which need to be serviced, when an interrupt has been issued to said processor by one of said peripheral devices; and
servicing all of said interrupt requests by said processor.
20. A computer program product as recited in claim 19 , further comprising computer readable program code means embodied therein for causing the computer to supply an interrupt from the peripheral devices to the processor, when the processor changes activity states from a first activity state to a second activity state.
21. A computer program product as recited in claim 20 , wherein the peripheral has a plurality of urgency states, further comprising computer readable program code for evaluating an activity state of the processor against the urgency state of a peripheral device, to determine whether said peripheral device issues an interrupt.
22. A computer program product as recited in claim 21 , wherein if said urgency state of a peripheral device is low, said peripheral device issues an interrupt to said processor only if said activity state of said processor is other than low.
23. A computer program product as recited in claim 19 , further comprising computer readable program code means embodied therein for detecting the activity state of the processor.
24. A computer program product as recited in claim 19 , further comprising computer readable program code for setting the urgency level of each of the peripherals that have been serviced to a lowest urgency level after the peripheral has been serviced.
25. A computer program product as recited in claim 19 , comprising computer readable program code wherein the activity states of the processor are represented by at least one bit output of the processor.
26. A computer program product as recited in claim 19 , further comprising computer readable program code wherein the activity states of the processor are represented by at least one output word generated by the processor.
27. A computer program product as recited in claim 19 , comprising computer readable program code for detecting the processor state as a state selected from active, idle and sleep.