Apparatus with improved layers of group III-nitride semiconductor
View Patent ↗An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.
1. An apparatus, comprising:
a crystalline substrate having a top surface;
a crystalline semiconductor layer comprising group III-nitride and being located on the top surface, the crystalline semiconductor layer having first and second surfaces, a plurality of lattice defects having first ends on the first surface, the second surface being separated from the top surface by semiconductor of the crystalline semiconductor layer, the entire portion of the first surface between the defects being next to the top surface; and
a plurality of dielectric regions located on the second surface, each defect threading the crystalline semiconductor layer and having a second end covered by a different one of the dielectric regions, each dielectric region being distant from the other dielectric regions and covering an end of only one threading defect.
2. The apparatus of claim 1 , wherein the crystalline substrate is lattice-mismatched to the crystalline semiconductor layer.
3. The apparatus of claim 2 , wherein the lattice-mismatched substrate comprises sapphire.
4. The apparatus of claim 2 , wherein the top surface is planar.
5. The apparatus of claim 4 , wherein the second surface of the crystalline semiconductor layer is smooth.
6. The apparatus of claim 1 , wherein the each dielectric region is a cap comprising an oxide of gallium.
7. The apparatus of claim 1 , wherein the dielectric regions comprise metal oxide.
8. The apparatus of claim 1 , wherein the group III-nitride comprises Ga, Al, or In.
9. The apparatus of claim 1 , wherein a concentration of metal atoms in the lattice defects is higher than in surrounding semiconductor matrix of the crystalline semiconductor layer.
10. The apparatus of claim 1 , further comprising a conductor in contact with the second surface and configured to transmit a current to the layer.
11. The apparatus of claim 1 , wherein the lattice defects are electrically passivated.
12. The apparatus of claim 11 , wherein the substrate is c-plane sapphire.