DMA engine for fetching words in reverse bit order
Presented herein is a direct memory access engine for providing data words in reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order. A set of multiplexers reverses the bit positions of the words in the local buffer.
1 . A method for providing a plurality of sequential data words, said method comprising:
receiving a command to provide the plurality of sequential data words, wherein the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word;
fetching a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word;
storing the sequential portion;
transmitting at least a portion of the last data word in reverse bit position order; and
transmitting at least a portion of the intermediate data words after transmitting at least the portion of the last data word in reverse bit position order.
2 . The method of claim 1 , further comprising:
fetching another sequential portion of the sequential data words, the another sequential portion comprising a second intermediate data word, immediately followed by one or more data words, immediately followed by a third intermediate data word, the third intermediate data word immediately preceding the first intermediate word;
storing the another sequential portion;
transmitting at least a portion of the third intermediate word in reverse bit position order; and
transmitting at least a portion of the second intermediate word after transmitting at least the portion of the third intermediate word in reverse bit position order.
3 . The method of claim 1 , wherein storing further comprises:
storing the sequential portion in a memory, the memory having a beginning address and an ending address, and wherein at least the portion of the last data word is stored at the ending address and wherein at least the portion of the first intermediate word is stored in the beginning address.
4 . The method of claim 3 , wherein the memory is characterized by a width, and the data words are characterized by a width, the width of the memory being smaller than the width of the data words.
5 . The method of claim 3 , wherein the last data word comprises at least the portion of the last data word and at least another portion, wherein at least the portion comprises the least significant bits of the last data word, and wherein the at least another portion comprises the most significant bits of the last data word, and wherein storing the portion further comprises:
storing the at least another portion of the last data word at an address preceding the ending address.
6 . The method of claim 5 , further comprising:
transmitting the at least another portion of the last word in reverse bit position order after transmitting at least the portion of the last word in reverse bit position order.
7 . The method of claim 1 , wherein the one or more data words comprise a predetermined number of data words.
8 . The method of claim 1 , wherein the plurality of sequential data words stores a slice group.
9 . A system for providing a plurality of sequential data words, said method comprising:
a state logic machine for receiving a command to provide the plurality of sequential of sequential data words, the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word;
a memory controller for fetching a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word;
a local buffer for storing the sequential portion; and
a plurality of multiplexers for reversing bit positions of at least a portion of the last data word and reversing bit positions of at least a portion of the intermediate data word;
a port for transmitting at least a portion of the last data word in the reverse bit position order and transmitting at least a portion of the intermediate data word in reverse bit position order after transmitting at least the portion of the last data word.
10 . The system of claim 9 , wherein:
the memory controller fetches another sequential portion of the sequential data words, the another sequential portion comprising a second intermediate data word, immediately followed by one or more data words, immediately followed by a third intermediate data word, the third intermediate data word immediately preceding the first intermediate word;
the local buffer stores the another sequential portion; and
the port transmits at least a portion of the third intermediate word and transmits at least a portion of the second intermediate word after transmitting at least the portion of the third intermediate word.
11 . The system of claim 9 , wherein the local buffer is associated with a beginning address and an ending address, and wherein a memory location at the ending address stores at least the portion of the last data word and wherein a memory location at the beginning address stores at least the portion of the first intermediate word.
12 . The system of claim 11 , wherein the local buffer is characterized by a width, and the data words are characterized by a width, the width of the local buffer being smaller than the width of the data words.
13 . The system of claim 11 , wherein the last data word comprises at least the portion of the last data word and at least another portion, wherein at least the portion comprises the least significant bits of the last data word, and wherein the at least another portion comprises the most significant bits of the last data word, and wherein a memory location at an address preceding the ending address stores the at least another portion of the last data word.
14 . The system of claim 13 , wherein the port transmits the at least another portion of the last word after transmitting at least the portion of the last word.
15 . The system of claim 9 , wherein the one or more data words comprise a predetermined number of data words.
16 . The system of claim 9 , wherein the plurality of sequential data words stores a slice group.
17 . A system for decoding a slice group, said system comprising:
a compressed data buffer comprising a plurality of sequential data words, the plurality of sequential data words for storing a slice group;
a video decoder for decoding the slice group; and
a direct memory access engine for providing the slice group to the video decoder, the direct memory access engine comprising:
a state logic machine for receiving a command to provide the plurality of sequential data words and a control signal indicating reverse order from the video decoder, the plurality of sequential data words comprises a first data word and a last data word, and one or more data words between the first data word and the last data word;
a memory controller for fetching a sequential portion of the sequential data words, said sequential portion comprising a first intermediate word, the last word, and one or more data words between the intermediate word and the last word;
a local buffer for storing the sequential portion;
a plurality of multiplexers for reversing the bit positions of the first intermediate word and the last data word; and
a port for transmitting at least a portion of the last data word in reverse bit position order and transmitting at least a portion of the intermediate data words in reverse bit position order after transmitting at least the portion of the last data word.