Planar circuit optimization
View Patent ↗The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.
1. A photolithographic mask set comprising:
a master mask including a first pattern having features for forming part of a planar lightwave circuit, the first pattern including a featureless region disposed therein such that the planar lightwave circuit is incomplete; and,
a slave mask including a second pattern having features for completing the planar lightwave circuit.
2. A photo lithographic mask set according to claim 1 , wherein the second pattern is designed to correct systematic errors induced by the master mask.
3. A photo lithographic mask set according to claim 1 , wherein the second pattern has been experimentally optimized using a plurality of other slave masks.
4. A photo lithographic mask set according to claim 1 , wherein a perimeter of the featureless region and a perimeter of the slave mask have a same shape and dimensions.
5. A photo lithographic mask set according to claim 1 , wherein the master mask and the slave mask are written on different regions of a same plate.
6. A photo lithographic mask set according to claim 5 , wherein the slave mask is written at a periphery of the master mask.
7. A photo lithographic mask set according to claim 1 , wherein the master mask and the slave mask are written on different plates.
8. A photo lithographic mask set according to claim 7 , comprising a plurality of other slave masks written on the same plate as the slave mask.
9. A photo lithographic mask set according to claim 1 , wherein the first pattern is for providing a general layout of the planar lightwave circuit, and wherein the features in the second pattern are for tuning the planar lightwave circuit.
10. A photo lithographic mask set according to claim 1 , wherein the slave mask is for providing a modificator section selected for optimizing the planar lightwave circuit.
11. A photo lithographic mask set according to claim 10 , wherein the at least one modificator section includes a plurality of waveguides that are modified relative to a corresponding plurality of waveguides outside the modificator section.
12. A photo lithographic mask set according to claim 11 , wherein the modifications comprise at least one of an expanded width of a wave guide, a gap within a wave guide and a lateral offset between a section of a wave guide within the modificator section and a section of the wave guide outside the modificator section.
13. A photo lithographic mask set according to claim 12 , wherein the planar lightwave circuit comprises an arrayed wave guide grating having a plurality of waveguides of different lengths arranged in an arc on a substrate.
14. A photo lithographic mask set according to claim 13 , wherein the at least one modificator section substantially bisects the arc.
15. A method of utilizing a photo lithographic mask set, the method comprising the steps of:
(a) providing a photo lithographic mask set including a master mask and a slave mask, the master mask including a first pattern having features for forming part of a planar lightwave circuit and including a featureless region disposed within the first pattern such that the planar lightwave circuit is incomplete, the slave mask including a second pattern having features for completing the planar lightwave circuit;
(b) using the photo lithographic mask set to expose at least part of a substrate;
(c) processing the exposed substrate to fabricate the planar lightwave circuit;
(d) analyzing the fabricated planar lightwave circuit; and
(e) determining an optimized planar lightwave circuit in dependence upon the analysis.
16. A method according to claim 15 , comprising the step of fabricating the optimized planar lightwave circuit.
17. A method according to claim 15 , wherein step (b) comprises:
aligning the master mask above the substrate and exposing the substrate through the master mask; and,
aligning the slave mask above the substrate and exposing the substrate through the slave mask, the slave mask aligned such that features in the second pattern align with corresponding features in the first pattern on the substrate.
18. A method according to claim 15 , wherein step (d) comprises measuring at least one of phase and amplitude errors of the fabricated planar lightwave circuit.
19. A method according to claim 18 , wherein step (d) further comprises using the at least one measured error to design at least one correcting slave mask.
20. A method according to claim 19 , wherein step (d) further comprises repeating steps (b) though (d) for the at least one correcting slave mask.
21. A method according to claim 19 , comprising the step of writing a production mask from data from the master mask and the at least one correcting slave mask.
22. A method according to claim 15 , wherein step (e) comprises calculating a desired modification to the slave mask to modify a property of the planar lightwave circuit.
23. A method according to claim 15 , wherein step (b) comprises stitching the slave mask to the master mask about a periphery of the featureless region.
24. A method according to claim 15 , wherein step (b) comprises the step of exposing a resist layer formed on an optical core layer.