Circuit for reducing current mirror mismatch due to gate leakage current
View Patent ↗A current mirror that compensates for the effects of gate current leakage related to quantum mechanical tunneling of electrons. An embodiment of the current mirror of the present invention comprises a first reference current leg, first and second current mirror legs and a load leg. Current compensation devices are operable to provide current compensation components to offset the effects of gate current leakage. In one embodiment of the invention the current compensation components comprise P-type CMOS transistors.
1. A current mirror, comprising:
a first leg comprising a reference current source operable to generate a reference current;
a first mirror current leg comprising a first P-type CMOS transistor and a first N-type transistor;
a second mirror current leg comprising a second P-Type CMOS transistor and a second N-type transistor;
a load leg comprising a third P-type transistor and a load; and
compensation circuitry operable to compensate for gate current leakage in said first, second and third P-type CMOS transistors.
2. The current source according to claim 1 , wherein said reference current is passed through an N-type CMOS transistor connected in a diode configuration.
3. The current mirror according to claim 1 , wherein said compensation circuitry comprises first and second P-type compensation transistors.
4. The current mirror according to claim 3 , wherein said first compensation transistor is connected in a diode configuration and is operable to sense and provide a portion of a reference current that is lost due to gate current leakage of said first, second and third P-type CMOS transistors.
5. The current mirror according to claim 4 , wherein said second P-type compensation transistor generates a compensation current equal to the portion of the reference current that is lost due to the gate current leakage of said first, second and third P-type CMOS transistors.
6. The current mirror according to claim 5 , wherein said load comprises a charge pump circuit for a phase-locked loop.
7. The current mirror according to claim 5 , wherein said current mirror comprises at least three output current sources.
8. The current mirror according claim 7 , wherein current mirror comprises a first sensing transistor in a diode configuration and at least three compensation devices to compensate for gate current leakage in said first, second and third P-type CMOS transistors.
9. The current mirror according to claim 8 , wherein said compensation devices comprise P-type CMOS transistors.
10. The current mirror according to claim 9 , wherein said three output current sources each comprise at least one P-type CMOS transistor and wherein said compensation devices compensate for gate current leakage in said P-type CMOS transistors.
11. A method of operating a current mirror circuit having a reference leg, first and second mirror legs each comprising a P-type CMOS transistor and a N-type transistor, and a load leg comprising P-type CMOS transistor and a load comprising:
generating a reference current in said reference leg of said current mirror circuit;
using said reference current to control the flow of current in said first and second mirror legs and said load leg of said current mirror circuit;
compensating for gate current leakage in said P-type CMOS transistors in said first and second mirror legs and the load leg, thereby generating a current flow in said load leg equal to the current flow in said reference leg.
12. The method according to claim 11 , wherein said reference current is passed through an N-type CMOS transistor connected in a diode configuration.
13. The method according to claim 12 , wherein said compensation comprises first and second P-type compensation transistors.
14. The method according to claim 13 , wherein said first compensation transistor senses and generates a compensation current equal to the sum of all gate current leakage through the diode connection of the first P-type CMOS transistor in the first mirror leg of said all P-type CMOS transistors.
15. The method according to claim 14 , wherein said second P-type compensation transistor copies the compensation current from the first P-type compensation transistor and adds the compensation current to a mismatched output current.
16. The method according to claim 15 , wherein said load comprises a charge pump circuit for a phase-locked loop.
17. The method according to claim 15 , wherein said current mirror comprises at least three output current source legs.
18. The method according claim 17 , wherein said current mirror comprises at least three compensation devices plus the very first sensing compensation device to compensate for gate current leakage in said all legs containing a P-type CMOS transistor.
19. The method according to claim 18 , wherein said compensation devices comprise P-type CMOS transistors.
20. The method according to claim 19 , wherein said three output current source legs each comprise at least one P-type CMOS transistor and said three current compensation devices each provide compensation for all of said P-type CMOS transistors.