Almost-symmetric multiprocessor that supports high-performance and energy-efficient execution
One embodiment of the present invention provides a system for controlling execution of tasks in a multiprocessor system, which contains both a high-performance processor and an energy-efficient processor. Upon receiving a task to be executed on the multiprocessor system, the system determines whether to execute the task on the high-performance processor or the energy-efficient processor based on performance requirements for the task and/or energy usage considerations for the multiprocessor system. Next, the system executes the task on either the high-performance processor or the energy-efficient processor based on the determination.
1 . A method for controlling execution of tasks in a multiprocessor system, which contains both a high-performance processor and an energy-efficient processor, comprising:
receiving a task to be executed on the multiprocessor system;
determining dynamically whether to execute the task on the high-performance processor or the energy-efficient processor; and
executing the task on either the high-performance processor or the energy-efficient processor based on the determination.
2 . The method of claim 1 , wherein determining whether to execute the task on the high-performance processor or the energy-efficient processor involves considering performance requirements for the task and/or energy usage considerations for the multiprocessor system.
3 . The method of claim 1 , wherein determining whether to execute the task on the high-performance processor or the energy-efficient processor, or subsequently determining whether it is advantageous to move the task between the high-performance processor and the energy-efficient processor, involves considering at least one of the following:
whether the task has been tagged to execute on the high-performance processor;
whether the multiprocessor system is currently operating on battery power;
the current workload of the energy-efficient processor; and
the current thermal condition of the high-performance processor.
4 . The method of claim 1 , wherein executing the task on the high-performance processor involves first:
determining whether the high-performance processor is powered on; and
if not, powering on the high-performance processor.
5 . The method of claim 1 , wherein if the task is executed on the high-performance processor, the method further comprises:
determining whether it is advantageous to move the task to the energy-efficient processor; and
if so, moving the task to the energy-efficient processor.
6 . The method of claim 5 , wherein after moving the task to the energy-efficient processor, the method further comprises:
determining whether the high-performance processor is executing any other tasks; and
if not, powering down the high-performance processor.
7 . The method of claim 6 , wherein powering down the high-performance processor involves:
flushing cache entries from the high-performance processor; and
powering off the high-performance processor.
8 . The method of claim 6 , wherein powering down the high-performance processor involves moving the high-performance processor into a deep sleep state, in which the contents of caches are preserved, but other portions of the high-performance processor are powered off.
9 . The method of claim 1 , wherein if the task is executed on the energy-efficient processor, the method further comprises:
determining whether it is advantageous to move the task to the high-performance processor; and
if so, moving the task to the high-performance processor.
10 . The method of claim 9 , wherein determining whether it is advantageous to move the task to the high-performance processor involves considering whether the task is taking too long to execute on the energy-efficient processor.
11 . The method of claim 1 , wherein the method further comprises supporting a cache coherence protocol on the multiprocessor system, wherein the cache coherency protocol ensures that cache entries within the energy-efficient processor remain coherent with cache entries within the high-performance processor.
12 . The method of claim 1 , wherein the energy-efficient processor and the high-performance processor are “almost symmetric,” which means that they execute identical instruction sets and are consequently able to execute the same tasks, but provide different levels of performance.
13 . The method of claim 12 , wherein the energy-efficient processor and the high-performance processor are both able to run the operating system.
14 . The method of claim 1 , wherein the energy-efficient processor is integrated onto a bridge chip, which additionally contains core logic circuitry that ties together and coordinates operations of components in the multiprocessor system.
15 . The method of claim 1 , wherein the high-performance processor is located on a dedicated processor chip, which contains one or more processor cores.
16 . The method of claim 1 , wherein the high-performance processor and the energy-efficient processor are located the same semiconductor chip.
17 . The method of claim 1 , wherein determining whether to execute the task on the high-performance processor or the energy-efficient processor involves:
initially executing the task on the energy-efficient processor; and
subsequently moving the task to the high-performance processor if the task takes too long to execute on the energy-efficient processor.
18 . A multiprocessor system that supports both high-performance and energy-efficient execution, comprising:
a high-performance processor;
an energy-efficient processor; and
an execution control process, which is configured to,
determine dynamically whether to execute a task on the high-performance processor or the energy-efficient processor, and to
execute the task on either the high-performance processor or the energy-efficient processor based on the determination.
19 . The multiprocessor system of claim 18 , wherein the execution control process is configured to determine dynamically whether to execute the task on the high-performance processor or the energy-efficient processor based on performance requirements for the task and/or energy usage considerations for the multiprocessor system.
20 . The multiprocessor system of claim 18 , wherein while determining whether to execute the task on the high-performance processor or the energy-efficient processor, the execution control process is configured to consider at least one of the following:
whether the task has been tagged to execute on the high-performance processor;
whether the multiprocessor system is currently operating on battery power;
the current workload of the energy-efficient processor; and
the current thermal condition of the high-performance processor.
21 . The multiprocessor system of claim 18 , wherein before executing the task on the high-performance, the execution control process is configured to:
determine whether the high-performance processor is powered on; and
if not, to power on the high-performance processor.
22 . The multiprocessor system of claim 18 , wherein if the task is executed on the high-performance processor, the execution control process is configured to:
determine whether it is advantageous to move the task to the energy-efficient processor; and
if so, to move the task to the energy-efficient processor.
23 . The multiprocessor system of claim 22 , wherein after moving the task to the energy-efficient processor, the execution control process is configured to:
determine whether the high-performance processor is executing any other tasks; and
if not, to power down the high-performance processor.
24 . The multiprocessor system of claim 23 , wherein powering down the high-performance processor involves:
flushing cache entries from the high-performance processor; and
powering off the high-performance processor.
25 . The multiprocessor system of claim 23 , wherein powering down the high-performance processor involves moving the high-performance processor into a deep sleep state, in which the contents of caches are preserved, but other portions of the high-performance processor are powered off.
26 . The multiprocessor system of claim 18 , wherein if the task is executed on the energy-efficient processor, the execution control process is configured to:
determine whether it is advantageous to move the task to the high-performance processor; and
if so, to move the task to the high-performance processor.
27 . The multiprocessor system of claim 26 , wherein determining whether it is advantageous to move the task to the high-performance processor involves considering whether the task is taking too long to execute on the energy-efficient processor.
28 . The multiprocessor system of claim 18 , wherein the multiprocessor system additionally includes a cache coherence mechanism, wherein the cache coherence mechanism ensures that cache entries within the energy-efficient processor remain coherent with cache entries within the high-performance processor.
29 . The multiprocessor system of claim 18 , wherein the energy-efficient processor and the high-performance processor are “almost symmetric,” which means that they execute identical instruction sets and are consequently able to execute the same tasks, but provide different levels of performance.
30 . The multiprocessor system of claim 29 , wherein the energy-efficient processor and the high-performance processor are both able to run the execution control process.
31 . The multiprocessor system of claim 18 , wherein the energy-efficient processor is integrated onto a bridge chip, which additionally contains core logic circuitry that ties together and coordinates operations of components in the multiprocessor system.
32 . The multiprocessor system of claim 18 , wherein the high-performance processor is located on a dedicated processor chip, which contains one or more processor cores.
33 . The multiprocessor system of claim 18 , wherein the high-performance processor and the energy-efficient processor are located the same semiconductor chip.
34 . The multiprocessor system of claim 18 , wherein while determining whether to execute the task on the high-performance processor or the energy-efficient processor, the execution control process is configured to:
initially execute the task on the energy-efficient processor; and to
subsequently move the task to the high-performance processor if the task takes too long to execute on the energy-efficient processor.
35 . An operating system for a multiprocessor system, wherein the multiprocessor system contains both a high-performance processor and an energy-efficient processor, comprising:
a task assignment mechanism configured to determine dynamically whether to execute a task on the high-performance processor or the energy-efficient processor based on performance requirements for the task and/or energy usage considerations for the multiprocessor system; and
an execution mechanism configured to execute the task on either the high-performance processor or the energy-efficient processor based on the determination.
36 . The operating system of claim 35 , wherein the task assignment mechanism is configured to determine whether to execute the task on the high-performance processor or the energy-efficient processor based on performance requirements for the task and/or energy usage considerations for the multiprocessor system.
37 . A bridge circuit for use in a multiprocessor system that supports both high-performance and energy-efficient execution, comprising:
(a) an energy-efficient processor;
(b) logic circuitry that ties together and coordinates operations of components of the multiprocessor system; and
(c) logic circuitry supporting a process for determining whether an executable task should be executed on the energy-efficient processor or, alternatively, on a high-performance processor.