Method for fabricating a lateral metal-insulator-metal capacitor
View Patent ↗A lateral metal-insulator-metal capacitor fabricated with consistent dummy fill and slotting patterns that assure predictable and controlled performance from the metalization layout while conforming to process design rules.
1. A lateral metal-insulator-metal capacitor produced by a manufacturing method, said manufacturing method comprising:
selecting a predetermined number of metal layers for an integrated circuit process;
selecting a subset of layers, said subset comprising a first layer, from the predetermined number of metal layers for use in fabricating a lateral metal-insulator-metal capacitor;
imparting an active interdigitated finger pattern on the selected subset of layers, said interdigitated finger pattern having a first terminal and a second terminal;
defining a first consistent dummy pattern on said first layer within the confines of the active interdigitated finger pattern;
defining a second consistent dummy pattern around the periphery of the active interdigitated finger pattern; and
imparting the second consistent dummy pattern to all metal layers
wherein defining said second consistent dummy pattern comprises:
defining a border region free of metal of approximately one to four times the thickness of the dielectric layer between the topmost metal layer in the selected subset and the layer directly above that layer, said border region extending about the periphery of the interdigitated finger pattern and along interconnect feed-lines to the terminals thereof;
defining an alternating metal pattern outward from the border region; and
imparting the alternating metal pattern onto all of the layers in an offset manner consistent with process design rules; and
imparting the first consistent dummy pattern on the remaining metal layers.
2. The lateral metal-insulator-metal capacitor produced by the manufacturing method of claim 1 wherein defining a first consistent dummy pattern comprises defining an alternating metal pattern within the overlap portion of the interdigitated finger pattern.
3. The lateral metal-insulator-metal capacitor produced by the manufacturing method of claim 1 wherein said manufacturing method further comprises:
defining a ground plane substantially under the bottommost layer of the selected subset of layers; and
defining an electrical connection from the first terminal to the ground plane.
4. The lateral metal-insulator-metal capacitor produced by the manufacturing method of claim 3 wherein said manufacturing method further comprises defining a slotting pattern for placing voids in the ground plane that avoid the second terminal of the interdigitated finger pattern.
5. The lateral metal-insulator-metal capacitor produced by the manufacturing method of claim 4 wherein defining an electrical connection from the first terminal to the ground plane comprises:
defining a plurality of vias from a finger on said first terminal to the ground plane alternating with the placement of the voids; and
defining a plurality of vias from a base of the first terminal to the ground plane.
6. A lateral metal-insulator-metal capacitor comprising:
an active interdigitated finger pattern having a first terminal and a second terminal imparted on a selected subset of layers of an integrated circuit, said subset of layers being selected by:
selecting a predetermined number of metal layers for an integrated circuit process, and
selecting a subset of layers from the predetermined number of metal layers for use in fabricating a lateral metal-insulator-metal capacitor, said subset comprising a first layer;
a first consistent dummy pattern imparted on said first layer of the subset within the confines of the active interdigitated finger pattern;
said first consistent dummy pattern further imparted on the remaining metal layers;
a second consistent dummy pattern imparted to all metal layers around the periphery of the active interdigitated finger pattern wherein said second consistent dummy pattern comprises border region free of metal of approximately one to four times the thickness of the dielectric layer between the top-most metal layer in the selected subset and the layer directly above that layer, said border region extending about the periphery of the interdigitated finger pattern and along interconnect feed-lines to the terminals thereof; and
alternating metal pattern imparted onto all of the layers in an offset manner consistent with process design rules and extending outward from the border region.
7. The lateral metal-insulator-metal capacitor of claim 6 wherein the first consistent dummy pattern comprises an alternating metal pattern within the overlap of the interdigitated finger pattern.
8. The lateral metal-insulator-metal capacitor of claim 6 further comprising:
ground plane disposed substantially under the bottom-most layer of the selected subset of layers; and
electrical connection that connects the first terminal to the ground plane.
9. The lateral metal-insulator-metal capacitor of claim 8 further comprising voids in the ground plane placed according to a slotting pattern that avoids the second terminal of the interdigitated finger pattern.
10. The lateral metal-insulator-metal capacitor of claim 9 wherein the electrical connection that connects the first terminal to the ground plane comprises:
plurality of vias from a finger on said first terminal to the ground plane alternating with the placement of the voids; and
plurality of vias from a base of the first terminal to the ground plane.