Frequency-digital signal conversion circuit

1. A frequency-digital signal conversion circuit, comprising:

a frequency detecting means for detecting a frequency of an input clock signal;

a latch means for sampling and latching an output of the frequency detecting means; and

a digital signal generating means for receiving an output of the latch means and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal; and

an erroneous operation preventing means for performing a hysteresis operation in order to prevent the output signal of the latch means from oscillating at a logic threshold voltage, in case that the frequency detecting operation is completed while the frequency of the clock signal is converted into the digital signal so that the output signal of the latch means is changed from one level to another level.

2. The frequency-digital signal conversion circuit as recited in claim 1 , wherein the frequency detecting means includes:

a first detecting unit for detecting a high level period of the input clock signal; and

a second detecting unit for detecting a low level period of the input clock signal.

3. The frequency-digital signal conversion circuit as recited in claim 2 , wherein the first detecting unit includes:

a plurality of first resistors connected in series between a first PMOS transistor and a first NMOS transistor; and

a plurality of first transistors respectively connected in parallel with the first resistors, and

the second detecting unit includes:

a plurality of second resistors connected in series between a second PMOS transistor and a second NMOS transistor; and

a plurality of second transistors respectively connected in parallel with the second resistors,

the output signal and inverted output signal of the digital signal generating means being applied to gates of the first and second transistors, respectively.

4. The frequency-digital signal conversion circuit as recited in claim 2 , wherein the latch means includes:

a first latch unit for sampling and latching an output of the first detecting unit;

a second latch unit for sampling and latching an output of the second detecting unit; and

an output unit for logically combining the outputs of the first and second latch units to generate the output signal.

5. The frequency-digital signal conversion circuit as recited in claim 4 , wherein each of the first and second latch units includes:

a buffer unit for buffering the outputs of the first and second detecting units in order for a data hold time;

a first transmission unit for transmitting an output of the buffer unit in synchronization with a falling edge of the clock signal;

a first latch for latching an output of the first transmission unit;

a second transmission unit for transmitting an output of the first latch in synchronization with a rising edge of a next clock signal; and

a second latch for latching an output of the second transmission unit.

6. The frequency-digital signal conversion circuit as recited in claim 4 , wherein the output unit is provided with a logic gate for NORing the outputs of the first and second latch units.

7. The frequency-digital signal conversion circuit as recited in claim 1 , wherein the erroneous operation preventing means includes:

resistors connected between first and second PMOS transistors and a plurality of first and second resistors; and

an NMOS transistor and a PMOS transistor connected in parallel with the resistors, the output signal of the latch means being applied to gates of the NMOS and PMOS transistors.

8. The frequency-digital signal conversion circuit as recited in claim 1 , wherein the digital signal generating means is a shift register provided with a plurality of D flip-flops for receiving and shifting the output signals of the latch means according to the clock signal to generate the digital signal.