Pulse width modulation digital amplifier
View Patent ↗In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
1. A digital amplifier comprising:
a noise shaper for removing a quantization noise of received data to generate sound data of n bits, where n is an integer larger than one; and
a pulse width modulator for modulating a pulse width of output data in response to the sound data in a normal operation, the pulse width modulator including
a data selection circuit for performing either one of increase and decrease of the pulse width of the output data stage by stage at every period of a specific clock obtained by dividing a frequency of a basic clock of pulse width modulation by n to set the output data to a center output when a specific operation is indicated.
2. The digital amplifier according to claim 1 , wherein the specific operation is a detection of power-off, and the data selection circuit decreases the output data stage by stage at every period of the specific clock to set the output data to a lowest output after setting the output data to the center output.
3. The digital amplifier according to claim 1 , wherein the specific operation is a detection of power-on, the output data includes a P output and an N output complementary to each other, a phase of the P output is same as a phase of the N output until the data selection circuit sets the output data to the center output, and the phase of the P output is opposite to the phase of the N output after the data selection circuit sets the output data to the center output.
4. The digital amplifier according to claim 3 , wherein the pulse width modulator further includes an output selection circuit for generating, as the N output, a signal having the same phase as the phase of the P output until the data selection circuit sets the output data to the center output, and generating, as the N output, a signal obtained by inverting the P output after the data selection circuit sets the output data to the center output.
5. The digital amplifier according to claim 1 , wherein the specific operation is a detection of power-off, the output data includes a P output and an N output complementary to each other, a phase of the P output is opposite to a phase of the N output until the data selection circuit sets the output data to the center output, and the phase of the P output is same as the phase of the N output after the data selection circuit sets the output data to the center output.
6. The digital amplifier according to claim 5 , wherein the pulse width modulator further includes an output selection circuit for generating, as the N output, a signal obtained by inverting the P output until the data selection circuit sets the output data to the center output, and generating, as the N output, a signal having the same phase as the phase of the P output after the data selection circuit sets the output data to the center output.
7. The digital amplifier according to claim 1 , wherein the specific clock is a clock of the noise shaper.
8. The digital amplifier according to claim 1 , wherein the specific operation is a detection of stopping of the sound data, the output data includes a P output and an N output complementary to each other, a phase of the P output is opposite to a phase of the N output until the data selection circuit sets the output data to the center output.