IP Library Granted Patent US 7,490,187
Granted Patent B2
US 7,490,187 · App. 10/742,060 · Granted Feb 10, 2009

Hypertransport/SPI-4 interface supporting configurable deskewing

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Quick Facts
Patent No.
US 7,490,187
App. No.
10/742,060
Granted
Feb 10, 2009
Kind
B2
Abstract

A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.

Claims (77)

1. A dual mode digital interface that supports the HyperTransport Standard and at least one other interface standard, the dual mode digital interface comprising:

a physical interface operable to couple to a servicing media, the servicing media including a physical line for each of a plurality of data lines and a clock line;

a plurality of data line amplifiers communicatively coupled to the physical interface and operable to amplify incoming data received on the plurality of data lines;

a clock line amplifier communicatively coupled to the physical interface and operable to amplify a clock signal received on the clock line;

a plurality of data line deskew/sampling blocks communicatively coupled to the plurality of data line amplifiers, each operable to deskew and sample incoming data on a respective data line based upon the clock signal to produce deskewed data;

a data group deskew module communicatively coupled to the plurality of data line deskew/sampling blocks, the data group deskew module and operable to receive deskewed data from each of the plurality of data line deskew/sampling blocks and to remove inter data line skew from the deskewed data to produce received data; and

enablement control module that is operable to disable the plurality of data line deskew/sampling blocks and/or the data group deskew module when supporting one aspect of the HyperTransport Standard and to enable the plurality of data line deskew/sampling blocks and/or the data group deskew module when supporting the at least one other interface standard.

2. The dual mode digital interface of claim 1 , wherein:

the enablement control module is operable to disable the plurality of data line deskew/sampling blocks and the data group deskew module when operating according to a first portion of the HyperTransport Standard having first skew tolerances; and

the enablement control module is operable to enable the plurality of data line deskew/sampling blocks and the data group deskew module when operating according to a second portion of the HyperTransport Standard having second skew tolerances that are less stringent than the first skew tolerances.

3. The dual mode digital interface of claim 1 , wherein the at least one other interface standard includes the SPI-4 Standard.

4. The dual mode digital interface of claim 1 , wherein each of the plurality of data deskew/sampling blocks comprises:

a phase locked loop operable to receive the clock signal and to produce a plurality of clock phases;

a plurality of latches, each of which is operable to latch data based upon a respective clock phase of the plurality of clock phases received from the phase locked loop;

a sampling phase selection block operable to produce a control signal based upon the latch outputs; and

a multiplexer operably coupled to receive outputs of each of the plurality of latches and to select one of the outputs based upon the control signal received from the sampling phase selection block as its output.

5. The dual mode digital interface of claim 1 , wherein the data group deskew module comprises:

a plurality of groups of cascaded latches, each group operably coupled to receive as its input an output of a respective data deskew/sampling block;

a plurality of multiplexers corresponding to the plurality of groups of cascaded latches, each multiplexer operably coupled to receive outputs of each latch of its corresponding group of cascaded latches; and

a delay selection module operable to control the plurality of multiplexers to select, for each multiplexer, an output of one of its respective cascaded latches.

6. The dual mode digital interface of claim 1 , wherein the plurality of data line deskew/sampling blocks and the data group deskew module are set based upon a training sequence received from a link partner.

7. The dual mode digital interface of claim 6 , wherein the training sequence is received during assertion of a HyperTransport reset signal on the servicing media.

8. The dual mode digital interface of claim 6 , wherein the training sequence is received immediately after de-assertion of a HyperTransport reset signal on the servicing media.

9. The dual mode digital interface of claim 6 , wherein the training sequence is periodically received in a training interval.

10. The dual mode digital interface of claim 6 , wherein the training sequence is received during a HyperTransport CRC testing mode.

11. A method for extracting received data from a plurality of incoming digital streams while supporting the HyperTransport Standard and at least one other interface standard, the method comprising:

receiving incoming data streams on a corresponding plurality of data lines;

receiving a clock signal on a clock line;

amplifying the incoming data streams;

amplifying the clock signal;

when supporting a first aspect of the HyperTransport Standard, sampling each incoming data stream based upon the clock signal to produce the received data without deskewing the incoming data streams; and

when supporting the at least one other interface standard:

optionally deskewing and sampling each incoming data stream based upon the clock signal to produce a plurality of deskewed data streams; and

optionally removing inter data stream skew from the plurality of deskewed data streams to produce the received data.

12. The method of claim 11 , further comprising, when supporting a second aspect of the HyperTransport Standard having less stringent skew tolerances than skew tolerances of the first aspect of the HyperTransport Standard:

deskewing and sampling each incoming data stream based upon the clock signal to produce a plurality of deskewed data streams; and

removing inter data stream skew from the plurality of deskewed data streams to produce the received data.

13. The method of claim 11 , wherein the at least one other interface standard includes the SPI-4 Standard.

14. The method of claim 11 , further comprising determining deskew settings based upon a training sequence received from a link partner.

15. The method of claim 14 , wherein the training sequence is received during assertion of a HyperTransport reset signal on the servicing media.

16. The method of claim 14 , wherein the received training sequence is received immediately after de-assertion of a HyperTransport reset signal on the servicing media.

17. The method of claim 14 , wherein the received training sequence is periodically received in a training interval.

18. The method of claim 14 , wherein the training sequence is received during a HyperTransport CRC testing mode.

19. A digital interface that supports the HyperTransport Standard comprising:

a physical interface operable to couple to a servicing media, the servicing media including a physical line for each of a plurality of data lines and a clock line;

a plurality of data line amplifiers communicatively coupled to the physical interface and operable to amplify incoming data received on the plurality of data lines;

a clock line amplifier communicatively coupled to the physical interface and operable to amplify a clock signal received on the clock line;

a plurality of data line deskew/sampling blocks communicatively coupled to the plurality of data line amplifiers, each operable to deskew and sample incoming data on a respective data line based upon the clock signal to produce deskewed data;

a data group deskew module communicatively coupled to the plurality of data line deskew/sampling blocks, the data group deskew module and operable to receive deskewed data from each of the plurality of data line deskew/sampling blocks and to remove inter data line skew from the deskewed data to produce received data; and

plurality of data line deskew/sampling blocks and/or the data group deskew module set with deskew settings determined based upon a training sequence received from a link partner.

20. The digital interface of claim 19 , wherein each of the plurality of data deskew/sampling blocks comprises:

a phase locked loop operable to receive the clock signal and to produce a plurality of clock phases;

a plurality of latches, each of which is operable to latch data based upon a respective clock phase of the plurality of clock phases received from the phase locked loop;

a sampling phase selection block operable to produce a control signal based upon the latch outputs; and

a multiplexer operably coupled to receive outputs of each of the plurality of latches and to select one of the outputs based upon the control signal received from the sampling phase selection block as its output.

21. The digital interface of claim 19 , wherein the data group deskew module comprises:

a plurality of groups of cascaded latches, each group operably coupled to receive as its input an output of a respective data deskew/sampling block;

a plurality of multiplexers corresponding to the plurality of groups of cascaded latches, each multiplexer operably coupled to receive outputs of each latch of its corresponding group of cascaded latches; and

a delay selection module operable to control the plurality of multiplexers to select, for each multiplexer, an output of one of its respective cascaded latches.

22. The digital interface of claim 19 , wherein the training sequence is received during assertion of a HyperTransport reset signal on the servicing media.

23. The digital interface of claim 19 , wherein the training sequence is received immediately after de-assertion of a HyperTransport reset signal on the servicing media.

24. The digital interface of claim 19 , wherein the training sequence is periodically received in a training interval.

25. The digital interface of claim 19 , wherein the training sequence is received during a HyperTransport CRC testing mode.

26. A method for extracting received data from a plurality of incoming digital streams transmitted according to the HyperTransport Standard, the method comprising:

receiving a training sequence from a HyperTransport Standard enabled link partner;

determining deskew settings based upon the training sequence;

receiving incoming data streams on a corresponding plurality of data lines;

receiving a clock signal on a clock line;

amplifying the incoming data streams;

amplifying the clock signal;

deskewing and sampling each incoming data stream based upon the clock signal to produce a plurality of deskewed data streams; and

removing inter data stream skew from the plurality of deskewed data streams to produce the received data based upon the training sequence.

27. The method of claim 26 , wherein the training sequence is received during assertion of a HyperTransport reset signal on the servicing media.

28. The method of claim 26 , wherein the training sequence is received immediately after de-assertion of a HyperTransport reset signal on the servicing media.

29. The method of claim 26 , wherein the training sequence is periodically received in a training interval.

30. The method of claim 26 , wherein the training sequence is received during a HyperTransport CRC testing mode.

31. The method of claim 26 , further comprising receiving a HyperTransport transaction from the link partner that does not carry transaction data but instead carries transition rich data.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2003
From: MOLL, LAURENT R.; GULATI, MANU
To: BROADCOM CORPORATION
Reel/Frame 014833/0888 →