IP Library Granted Patent US 6,933,787
Granted Patent B1
US 6,933,787 · App. 10/742,098 · Granted Aug 23, 2005

Linearized darlington amplifier

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Quick Facts
Patent No.
US 6,933,787
App. No.
10/742,098
Granted
Aug 23, 2005
Kind
B1
Abstract

An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal in response to an input signal. The common-base transistor may (i) be coupled between an output transistor of the Darlington transistor pair and the output signal and (ii) have a base configured to receive a frequency dependent reference voltage.

Claims (27)

1. An apparatus comprising:

a Darlington transistor pair configured to generate an output signal in response to an input signal; and

a common-base transistor (i) coupled between an output transistor of said Darlington transistor pair and said output signal and (ii) having a base configured to receive a frequency dependent reference voltage.

2. The apparatus of claim 1 , wherein said frequency dependent reference voltage is configured to optimize performance of said apparatus.

3. The apparatus according to claim 1 , wherein said frequency dependent reference voltage is generated by a reference circuit.

4. The apparatus according to claim 3 , wherein said reference circuit includes an emitter follower and an inductive element.

5. The apparatus according to claim 4 , wherein said reference circuit further includes a series RLC tank configured to optimize linearity, gain and stability performance.

6. The apparatus according to claim 3 , wherein said reference circuit is electronically tunable to control linearity of said apparatus.

7. The apparatus according to claim 1 , wherein said common-base transistor improves broadband linearity (IP3) of said apparatus.

8. The apparatus according to claim 1 , wherein said common-base transistor is configured in cascode with said output transistor.

9. The apparatus according to claim 1 , wherein said Darlington transistor pair further comprises an input transistor.

10. The apparatus according to claim 1 , wherein said common-base transistor is configured to adjust the phase of said output signal.

11. The apparatus according to claim 3 , wherein said reference circuit comprises a DC voltage reference configured to provide a DC bias to the base of said common-base transistor.

12. The apparatus according to claim 11 , wherein said reference circuit is further configured to provide a frequency dependent AC impedance to the base of said common-base transistor.

13. An apparatus comprising:

means for configuring a Darlington transistor pair to generate an output signal in response to an input signal; and

means for configuring a common-base transistor (i) coupled between an output transistor of said Darlington transistor pair and said output signal and (ii) having a base configured to receive a frequency dependent linearity reference voltage.

14. A method for implementing a linearized Darlington amplifier comprising the steps of:

(A) configuring a Darlington transistor pair to generate an output signal in response to an input signal; and

(B) coupling a common-base transistor between an output transistor of said Darlington transistor pair and said output signal, wherein a base of said common-base transistor is configured to receive a frequency dependent reference voltage.

15. The method of claim 14 , wherein said frequency dependent reference voltage is configured to optimize performance of said Darlington amplifier.

16. The method according to claim 14 , further comprising the step of:

generating said frequency dependent reference voltage with a reference circuit.

17. The method according to claim 14 , wherein said frequency dependent reference voltage is electronically tunable to control linearity of said Darlington amplifier.

18. The method according to claim 14 , wherein step (B) improves broadband linearity (IP3) of said Darlington amplifier.

19. The method according to claim 14 , wherein said common-base transistor is configured to adjust the phase of said output signal.

20. The method according to claim 14 , wherein step (B) is further configured to provide a frequency dependent AC impedance to the base of said common-base transistor.

Assignments (7)
MERGER Recorded Jun 16, 2016
From: RF MICRO DEVICES, INC.
To: QORVO US, INC.
Reel/Frame 039196/0941 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS (RECORDED 3/19/13 AT REEL/FRAME 030045/0831) Recorded Mar 30, 2015
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: RF MICRO DEVICES, INC.
Reel/Frame 035334/0363 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE TO SIRENZA MICRODEVICES, INC. PREVIOUSLY RECORDED ON REEL 014833 FRAME 0803. ASSIGNOR(S) HEREBY CONFIRMS THE STREET ADDRESS OF THE ASSIGNEE IS 522 ALMANOR AVENUE. Recorded Apr 25, 2013
From: KOBAYASHI, KEVIN W.
To: SIRENZA MICRODEVICES, INC.
Reel/Frame 030294/0695 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNOR TO SIRENZA MICRODEVICES, INC. PREVIOUSLY RECORDED ON REEL 021172 FRAME 0388. ASSIGNOR(S) HEREBY CONFIRMS THE NAME OF THE ASSIGNEE IS RF MICRO DEVICES, INC.. Recorded Apr 11, 2013
From: SIRENZA MICRODEVICES, INC.
To: RF MICRO DEVICES, INC.
Reel/Frame 030194/0944 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2013
From: RF MICRO DEVICES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 030045/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2008
From: SIRENZA MICRODEVICES
To: RF MICRO DEVICES, INC.
Reel/Frame 021172/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2003
From: KOBAYASHI, KEVIN W.
To: SIRENZA MICRODEVICES
Reel/Frame 014833/0803 →