Priority encoder circuit and method
View Patent ↗A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged in a logical order of priority receives a plurality of active matchline sense output signals. Each block of multiple match resolver circuits generates a flag signal and a local address corresponding to the highest priority active matchline sense output signal received. Control logic receives flag signals from the multiple match resolver circuits, and identifies the highest priority multiple match resolver circuit that has received an active matchline sense output signal. The control logic then disables all lower priority multiple match resolver circuits such that only the local address generated by the highest priority multiple match resolver circuit is passed by the priority encoder. The flag signals are also decoded to provide a logical address of the highest priority multiple match resolver circuit. The passed local address and the logical address of the highest priority multiple match resolver circuit are concatenated to provide the global address of the highest priority active matchline sense output signal received by the priority encoder.
1. A priority encoder for generating a global address of a highest priority match signal from a plurality of match signals, comprising:
a plurality of match resolver circuits for generating a plurality of local match addresses in response to the plurality of match signals, each of the plurality of local match addresses having a distinct priority level; and,
a logic circuit for determining an address of a highest priority level local match address, and for generating a feedback enable signal corresponding to the highest priority level local match address for enabling transfer of the highest priority level local match address from one of the plurality of match resolver circuits, the global address being a concatenation of the address and the highest level priority local match address.
2. The priority encoder of claim 1 , wherein each of the plurality of match resolver circuits receives a set of the plurality of match signals for generating one local match address corresponding to the highest priority level match signal and one flag signal corresponding to the distinct priority level of the one local match address.
3. The priority encoder of claim 2 , wherein the logic circuit includes a further match resolver circuit for receiving the flag signals from the plurality of match resolver circuits and generating the address of a highest priority level flag signal.
4. The priority encoder of claim 1 , wherein each of the plurality of match resolver circuits is coupled to common address lines for carrying the highest priority level local match address.
5. The priority encoder of claim 4 , wherein the feedback enable signal enables the one of the plurality of match resolver circuits to drive the common address lines with the highest priority level local match address.
6. The priority encoder of claim 5 , wherein each of the plurality of match resolver circuits includes
an input circuit for receiving a set of the plurality of match signals in an order of priority and for generating corresponding intermediate outputs and the one flag signal,
a masking circuit for disabling the intermediate outputs corresponding to match signals having a priority level lower than a highest priority match signal, and,
an address encoding circuit for receiving the intermediate outputs and for generating the local match address corresponding to the highest priority match signal.
7. The priority encoder of claim 6 , wherein the address encoding circuit includes a tri-state buffer for driving the address onto the common address lines in response to a feedback enable signal.
8. A method for determining a global address of a highest priority level match signal from a plurality of match signals, comprising:
a) generating a plurality of local match addresses in response to the plurality of match signals, each local match address having a predetermined priority level and an address corresponding to a source of generation of the local match address;
b) determining a highest priority level local match address from the plurality of local match addresses;
c) generating a feedback enable signal corresponding to the highest priority level local match address for enabling transfer of the highest priority level local match address; and
d) concatenating the highest priority level local match address to the address to provide the global address.
9. The method of claim 8 , wherein the step of generating includes providing a set of the plurality of match signals to a corresponding match resolver circuit, the corresponding match resolver circuit providing the local match address corresponding to a highest priority level match signal of the set of match signals.
10. The method of claim 8 , wherein the step of generating includes generating a flag signal corresponding to each generated local match address, each flag signal having the predetermined priority level.
11. The method of claim 10 , wherein the step of determining includes receiving flag signals for determining a highest priority flag signal.
12. The method of claim 11 , further including a step of enabling a match resolver circuit corresponding to the highest priority flag signal to provide the local match address of the highest priority flag signal.
13. The method of claim 8 , wherein the local match address is a lower significant portion of the global address and the address is a higher significant portion of the global address.