IP Library Granted Patent US 7,502,601
Granted Patent B2
US 7,502,601 · App. 10/743,218 · Granted Mar 10, 2009

Power amplifier with digital power control and associated methods

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Quick Facts
Patent No.
US 7,502,601
App. No.
10/743,218
Granted
Mar 10, 2009
Kind
B2
Abstract

In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.

Claims (32)

1. A method of amplifying RF signals comprising:

providing an RF power amplifier formed on an integrated circuit;

storing a plurality of ramp profiles in the integrated circuit;

receiving one or more digital control signals containing power control data from a controller that is external to the integrated circuit, wherein the control signals are received over a digital interface; and

selecting one of the ramp profiles using a digital signal processor to vary the output power of the RF power amplifier based on a desired output power level relating to one or more of the digital control signals from the controller.

2. The method of claim 1 , further comprising sensing one or more properties related to the integrated circuit.

3. The method of claim 2 , wherein one of the one or more properties sensed is the temperature of the integrated circuit.

4. The method of claim 2 , wherein one of the one or more properties sensed is the voltage of a battery.

5. The method of claim 2 , wherein the ramp profile is selected based on a received power control signal and a sensed property.

6. The method of claim 1 , further comprising using the selected ramp profile to generate a power control signal for controlling the output power of the RF power amplifier.

7. The method of claim 6 , further comprising providing a digital to analog convener for generating the power control signal.

8. The method of claim 1 , further comprising generating a clock signal for use by the digital signal processor.

9. The method of claim 8 , further comprising dividing an RF input signal to generate the clock signal.

10. A method of controlling a wireless communication device comprising:

providing a baseband controller;

providing an integrated circuit having an RF power amplifier, memory, a digital interface, and an RF input, all formed using the integrated circuit;

forming a digital signal processor using the integrated circuit;

storing a plurality of ramp profiles in the memory formed using the integrated circuit;

sending a digital power control signal from the baseband controller to the integrated circuit using the digital interface, wherein the digital power control signal relates to a desired output power level;

selecting one of the plurality of ramp profiles based on the digital power control signal received from the baseband controller; and

using the selected ramp profile to control the output power of the RF power amplifier.

11. The method of claim 10 , further comprising providing a digital interface between the baseband controller and the integrated circuit.

12. The method of claim 10 , further comprising providing a serial interface between the baseband controller and the integrated circuit.

13. The method of claim 10 , further comprising:

sensing the temperature of the integrated circuit; and

selecting the ramp profile based on the power control signal and the sensed temperature.

14. The method of claim 10 , further comprising:

sensing the battery voltage of the wireless communication device; and

selecting the ramp profile based on the power control signal and the sensed battery voltage.

15. The method of claim 10 , wherein the digital signal processor selects one of the plurality of ramp profiles.

16. The method of claim 10 , further comprising downloading ramp profiles to the digital signal processor.

17. The method of claim 10 , further comprising providing a digital to analog converter using the integrated circuit for generating a control signal based on the selected ramp profile.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2014
From: BLACK SAND TECHNOLOGIES, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 034077/0072 →
RELEASE OF SECURITY INTEREST Recorded Sep 12, 2014
From: SILICON LABORATORIES INC.
To: BLACK SAND TECHNOLOGIES INC.
Reel/Frame 033729/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2014
From: SILICON LABORATORIES INC.
To: BLACK SAND TECHNOLOGIES, INC.
Reel/Frame 033500/0122 →
RELEASE OF SECURITY INTEREST Recorded Jun 30, 2014
From: COMERICA BANK
To: BLACK SAND TECHNOLOGIES, INC.
Reel/Frame 033258/0225 →
MERGER Recorded Jun 27, 2014
From: WAVEFORM ACQUISITION CORPORATION
To: BLACK SAND TECHNOLOGIES, INC.
Reel/Frame 033247/0787 →
SECURITY AGREEMENT Recorded Mar 5, 2009
From: BLACK SAND TECHNOLOGIES, INC.
To: COMERICA BANK
Reel/Frame 022343/0475 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2008
From: SILICON LABORATORIES INC.
To: BLACK SAND TECHNOLOGIES, INC.
Reel/Frame 021243/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2003
From: DUPUIS, TIMOTHY J.
To: SILICON LABORATORIES, INC.
Reel/Frame 014847/0249 →