IP Library Granted Patent US 7,191,257
Granted Patent B2
US 7,191,257 · App. 10/743,416 · Granted Mar 13, 2007

System and method for real-time processing of nondeterministic captured data events

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Quick Facts
Patent No.
US 7,191,257
App. No.
10/743,416
Granted
Mar 13, 2007
Kind
B2
Abstract

A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.

Claims (50)

1. A system, comprising:

data capture logic configured to capture data events from a nondeterministic data bus;

a system memory including a plurality of addressable locations, wherein a subset of said plurality of addressable locations is configured as a data event buffer;

a direct memory access (DMA) transfer engine coupled to said data capture logic and to said system memory and configured to perform a DMA transfer operation of said captured data events from said data capture logic to a region of said data event buffer as portions of said captured data events become available from said data capture logic; and

an application configured to retrieve captured data events from said region of said data event buffer without said DMA transfer operation of said captured data events from said data capture logic to said region being stopped, such that said application is configured to display said retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on said nondeterministic data bus.

2. The system as recited in claim 1 , wherein said data event buffer is configured as a circular data event buffer.

3. The system as recited in claim 1 , wherein said data event buffer is configured as a linear data event buffer.

4. The system as recited in claim 1 , wherein said DMA transfer engine is further configured to convey an indication of data readiness to said application after transferring a given number of said captured data events to said data event buffer.

5. The system as recited in claim 1 , wherein said application is further configured to request an indication of data readiness after a given period of time has elapsed without receiving a signal indicative of data readiness.

6. The system as recited in claim 1 , wherein in response to said region of said data event buffer being filled, said DMA transfer engine is further configured to perform said DMA transfer operation to a different region of said data event buffer without said DMA transfer operation being stopped.

7. The system as recited in claim 1 , wherein said data event buffer is allocated within a kernel address space.

8. The system as recited in claim 1 , wherein said nondeterministic data bus conforms to the IEEE-488 General Purpose Interface Bus (GPJB) standard.

9. The system as recited in claim 1 , wherein said data capture logic is further configured to assign a respective sample index value to each of said captured data events, and wherein said DMA transfer engine is further configured to pause said DMA transfer operation in response to detecting that the respective sample index value corresponding to one of said captured data events matches a selected sample index value.

10. The system as recited in claim 1 , wherein said data capture logic is further configured to store said captured data events in a capture buffer, wherein in response to detecting an overflow of said capture buffer, said data capture logic is further configured to stop capturing data events without said DMA transfer operation being stopped.

11. A method, comprising:

capturing data events from a nondetermimstic data bus, wherein said capturing comprises storing said data events in a capture buffer;

a DMA transfer engine performing a DMA transfer of said captured data events from said capture buffer to a region of a data event buffer as portions of said captured data events become available;

retrieving captured data events from said region of said data event buffer without stopping said DMA transfer of said captured data events from said capture buffer to said region; and

displaying said retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on said nondeterministic data bus.

12. The method as recited in claim 11 , wherein said data event buffer is configured as a circular data event buffer.

13. The method as recited in claim 11 , wherein said data event buffer is configured as a linear data event buffer.

14. The method as recited in claim 11 , further comprising conveying an indication of data readiness to an application after transferring a given number of said captured data events to said data event buffer.

15. The method as recited in claim 11 , further comprising requesting an indication of data readiness of said captured data events in said data event buffer after a given period of time has elapsed without receiving a signal indicative of data readiness.

16. The method as recited in claim 11 , further comprising:

detecting that said region of said data event buffer is full during said transferring; and

in response to said detecting that said region is full, transferring said captured data events to a different region of said data event buffer without stopping.

17. The method as recited in claim 11 , wherein said data event buffer is allocated within a kernel address space.

18. The method as recited in claim 11 , wherein said nondeterministic data bus conforms to the IEEE-488 General Purpose Interface Bus (GPIB) standard.

19. The method as recited in claim 11 , further comprising:

assigning a respective sample index value to each of said captured data events prior to transferring each said captured data event;

prior to transferring a given captured data event, detecting that said respective sample index value corresponding to said given captured data event matches a selected sample index value; and

in response to detecting said match, pausing said transferring of said captured data events.

20. The method as recited in claim 11 , further comprising:

storing said captured data events in a capture buffer prior to said transferring;

detecting an overflow of said capture buffer; and

in response to detecting said overflow, stopping said capturing of said data events without stopping said transferring of said captured data events.

21. A tangible, computer-accessible storage medium comprising program instructions, wherein said program instructions are computer-executable to:

enable data capture logic configured to capture data events from a nondeterministic data bus;

configure a direct memory access (DMA) transfer engine to perform a DMA transfer operation of said captured data events to a region of a data event buffer as portions of said captured data events become available;

retrieve captured data events from said region of said data event buffer without said DMA transfer operation of said captured data events to said region being stopped; and

display said retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on said nondeterministic data bus.

22. The computer-accessible medium as recited in claim 21 , wherein said data event buffer is configured as a circular data event buffer.

23. The computer-accessible medium as recited in claim 21 , wherein said data event buffer is configured as a linear data event buffer.

24. The computer-accessible medium as recited in claim 21 , wherein said DMA transfer engine is further configured to convey an indication of data readiness to an application after transferring a given number of said captured data events to said data event buffer.

25. The computer-accessible medium as recited in claim 21 , wherein said program instructions are further executable to request an indication of data readiness after a given period of time has elapsed without receiving a signal indicative of data readiness.

26. The computer-accessible medium as recited in claim 21 , wherein in response to said region of said data event buffer being filled, said DMA transfer engine is further configured to perform said DMA transfer operation to a different region of said data event buffer without said DMA transfer operation being stopped.

27. The computer-accessible medium as recited in claim 21 , wherein said data event buffer is allocated within a kernel address space.

28. The computer-accessible medium as recited in claim 21 , wherein said nondeterministic data bus conforms to the IEEE-488 General Purpose Interface Bus (GPIB) standard.

29. The computer-accessible medium as recited in claim 21 , wherein said data capture logic is further configured to assign a respective sample index value to each of said captured data events, and wherein said DMA transfer engine is further configured to pause said DMA transfer operation in response to detecting that the respective sample index value corresponding to one of said captured data events matches a selected sample index value.

30. The computer-accessible medium as recited in claim 21 , wherein said data capture logic is further configured to store said captured data events in a capture buffer, wherein in response to detecting an overflow of said capture buffer, said data capture logic is further configured to stop capturing data events without said DMA transfer operation being stopped.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2003
From: KHAN, KHASID M. ALI; BAK, BORIS M.; AIKEN, CRAIG A.; WIDJAJA, TONY
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 014842/0113 →