Optimizing designing apparatus of integrated circuit, optimizing designing method of integrated circuit, and storing medium in which program for carrying out optimizing designing method of integrated circuit is stored
View Patent ↗It is an object of the present invention to provide a method, an apparatus and a program having high optimization precision and capable of obtaining an answer required by a designer in a short time by combining optimization between individual transistors and optimization as the entire circuit, or by appropriately combining judgment of an operation region, an analysis of the operation region and a SWEEP sensitivity analysis when the optimization is carried out. An optimizing designing apparatus of an integrated circuit for designing a circuit, comprises operation region judging means for adjusting an operation region (linear region, saturation region) of the circuit, operation region analysis means for displaying liner characteristics (Ids-Vgs characteristics) of the circuit and saturation characteristics (Ids-Vds characteristics) of the circuit, and SWEEP sensitivity analysis means for displaying variation in output characteristics of the circuit.
1. An optimizing designing apparatus of an integrated circuit for designing a circuit, comprising:
operation region judging means which carries out analysis of operation of said circuit, which extracts node voltage of the circuit and transistor current Ids of the circuit obtained as a result of the analysis, which converts the extracted node voltage into voltages Vds and Vgs between nodes of a transistor using a circuit topology information, and which judges an operation region including a linear region and a saturation region using threshold voltage, the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor;
operation region analysis means which carries out DC analysis or TRAN analysis of the circuit, which extracts node voltage of the circuit and the transistor current Ids of the circuit obtained as a result of the analysis by the operation region analysis means, which converts the extracted node voltage into the voltages Vds and Vgs between the nodes of the transistor using the circuit topology information, and which displays linear characteristics including Ids-Vgs characteristics and saturation characteristics including Ids-Vds characteristics using the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor; and
SWEEP sensitivity analysis means which displays variation in output characteristics of said circuit when the circuit parameter including gate width W and gate length L is varied by ±α(%).
2. An optimizing designing apparatus of an integrated circuit for designing a second circuit having the same function as that of a first circuit when producing process, physical specification of a semiconductor is changed, comprising:
operation region judging means which carries out analysis of operation of said circuit, which extracts node voltage of the circuit and transistor current Ids of the circuit obtained as a result of the analysis by the operation region judging means, which converts the extracted node voltage into voltages Vds and Vgs between nodes of a transistor using a circuit topology information, and which judges an operation region including linear region and saturation region using threshold voltage, the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor;
operation region analysis means which carries out DC analysis or TRAN analysis of the circuit, which extracts node voltage of the circuit and the transistor current Ids of the circuit obtained as a result of the analysis by the operation region analysis means, which converts the extracted node voltage into the voltages Vds and Vgs between the nodes of the transistor using the circuit topology information, and which displays linear characteristics including Ids-Vgs characteristics and saturation characteristics including Ids-Vds characteristics using the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor; and
LOCAL optimizing means for carrying out the optimization of each transistor of said second circuit corresponding to a transistor constituting said first circuit using a circuit simulator.
3. An optimizing designing apparatus of an integrated circuit for designing a second circuit having the same function as that of a first circuit when producing process, physical specification of a semiconductor is changed, comprising:
operation region judging means which carries out analysis of operation of said circuit, which extracts node voltage of the circuit and transistor current Ids of the circuit obtained as a result of the analysis by the operation region judging means, which converts the extracted node voltage into voltages Vds and Vgs between nodes of a transistor using circuit topology information, and which judges an operation region including linear region and saturation region using threshold voltage, the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor;
SWEEP sensitivity analysis means which displays variation in output characteristics of said circuit when the circuit parameter including gate width W and gate length L is varied by ±α(%); and
GLOBAL optimizing means which designates an arbitrary transistor constituting said second circuit, and which optimizes said second circuit by optimizing the designated transistor using a circuit simulator.
4. An optimizing designing apparatus of an integrated circuit for designing a second circuit having the same function as that of a first circuit when producing process, physical specification of a semiconductor is changed, comprising:
operation region judging means which carries out analysis of operation of said circuit, which extracts node voltage of the circuit and transistor current Ids of the circuit obtained as a result of the analysis by the operation region judging means, which converts the extracted node voltage into voltages Vds and Vgs between nodes of a transistor using circuit topology information, and which judges an operation region including linear region and saturation region using threshold voltage, the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor;
operation region analysis means which carries out DC analysis or TRAN analysis of the circuit, which extracts node voltage of the circuit and the transistor current Ids of the circuit obtained as a result of the analysis by the operation region analysis means, which converts the extracted node voltage into the voltages Vds and Vgs between the nodes of the transistor using the circuit topology information, and which displays linear characteristics including Ids-Vgs characteristics and saturation characteristics including Ids-Vgs characteristics using the transistor current Ids and the voltages Vds and Vgs between the nodes of the transistor;
LOCAL optimizing means for carrying out the optimization of each transistor of said second circuit corresponding to a transistor constituting said first circuit using a circuit simulator; SWEEP sensitivity analysis means which displays variation in output characteristics of said circuit when the circuit parameter including gate width W and gate length L is varied by ±α(%); and
GLOBAL optimizing means which designates an arbitrary transistor constituting said second circuit, and which optimizes said second circuit by optimizing the designated transistor using a circuit simulator.