IP Library Granted Patent US 7,410,851
Granted Patent B2
US 7,410,851 · App. 10/746,334 · Granted Aug 12, 2008

Low voltage superjunction MOSFET

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Quick Facts
Patent No.
US 7,410,851
App. No.
10/746,334
Granted
Aug 12, 2008
Kind
B2
Abstract

A power semiconductor switching device such as a power MOSFET that includes breakdown voltage enhancement regions formed by self-alignment.

Claims (14)

1. A process for manufacturing a power semiconductor device, comprising:

providing a semiconductor body of a first conductivity and first charge level;

forming a plurality of spaced gate structures on said semiconductor body, each gate structure including at least a gate insulation body, and a gate electrode;

implanting first dopants of a second conductivity into said semiconductor body through spaces between said gate structures;

diffusing said first dopants of said second conductivity to form a plurality of channel regions;

implanting dopants of said first conductivity into said channel regions through said spaces between said gate structures to form source implant regions;

implanting second dopants of said second conductivity through said spaces between said gate structures to a depth below the depth of said channel regions; and

diffusing said second dopants to form breakdown voltage enhancing regions having a second charge level; wherein

said first charge level and said second charge level are such that said breakdown voltage enhancing regions and said semiconductor body deplete one another under application of a reverse voltage.

2. The process of claim 1 , wherein said second dopants are diffused until said each channel region merges with a respective breakdown voltage enhancing region.

3. The process of claim 1 , wherein said second dopants are diffused such that the lateral dimension of each said breakdown enhancing region is less than a respective channel region disposed vertically adjacent thereto.

4. The process of claim 1 , further comprising forming an insulation body over each gate structure prior to implanting said second dopants, each insulation body being spaced from another insulation body, and implanting said second dopants through said spaces between said insulation bodies.

5. The process of claim 4 , further comprising implanting third dopants of said second conductivity in each channel region through spaces between said insulation bodies to form contact regions.

6. The process of claim 4 , further comprising forming a depression into each channel region prior to implanting said second dopants.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2003
From: HENSON, TIMOTHY; CAO, JIANJUN
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 014849/0610 →