Method of fabricating semiconductor device
View Patent ↗There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution -limit of an exposure system, thereby enlarging a floating gate width.
1. A method of fabricating a semiconductor device made up of memory cells each having a control gate formed above a floating gate, said method comprising the step of:
forming a resist pattern having a group of openings disposed at a plurality of spots, respectively, on an electrically conductive film, serving as the floating gates, formed across a substrate;
baking the resist pattern to thereby cause deformation due to thermal flow to occur thereto and causing the group of the openings to be linked with each other;
etching a portion of the electrically conductive film, in the group of the openings linked with each other, and forming end faces of the respective floating gates, along the direction of a gate width thereof, at respective linkage parts;
forming the control gate, extended in the direction of the gate width of the respective floating gates, above a portion of the electrically conductive film, defining the end faces of the respective floating gates, with an insulating film interposed therebetween; and
selectively etching the electrically conductive film using the control gates as masks to thereby form the floating gate under the respective control gates.
2. A method of fabricating a semiconductor device according to claim 1 , wherein the group of the openings of the resist pattern are formed so as to be arranged in line along a direction crossing the respective control gates at right angles, and a spacing between the respective groups of the openings is about half a length of the respective control gates.
3. A method of fabricating a semiconductor device according to claim 1 , wherein a length of the group of the openings, along a direction in which the respective control gates are extended, is a length corresponding to the resolution limit of a pattern exposure system.
4. A method of fabricating a semiconductor device according to claim 1 , wherein a baking temperature for the resist pattern is about 135° C.