Semiconductor storage device
View Patent ↗A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.
1. A semiconductor storage device comprising:
a memory cell array having a plurality of memory cell transistors arranged in a matrix form and having storage values written therein by connecting/disconnecting first main electrodes of the memory cell transistors to/from a first power line;
a plurality of word lines respectively connected to control electrodes of the memory cell transistors along corresponding rows of the memory cell array;
a plurality of bit lines respectively connected to other main electrodes of the memory cell transistors along corresponding columns of the memory cell array;
a data line for selectively outputting a potential on the bit lines;
a select transistor of a first conductivity type having a first main electrode connected to a corresponding one of the bit lines, an other main electrode connected to the data line, and a control electrode having a corresponding select signal input thereto; and
a precharge transistor of a second conductivity type having a first main electrode connected to the corresponding one of the bit lines, an other main electrode connected to a second power line, and a control electrode having the corresponding select signal input thereto,
wherein the select transistor and the precharge transistor are both controlled by the corresponding select signal.
2. A semiconductor storage device comprising:
a memory cell array having a plurality of memory cell transistors arranged in a matrix form and having storage values written therein by connecting/disconnecting first main electrodes of the memory cell transistors to/from a first power line;
a plurality of word lines respectively connected to control electrodes of the memory cell transistors along corresponding rows of the memory cell array;
a plurality of bit lines respectively connected to other main electrodes of the memory cell transistors along corresponding columns of the memory cell array;
a data line for selectively outputting a potential on the bit lines;
a select transistor having a first main electrode connected to a corresponding one of the bit lines, an other main electrode connected to the data line, and a control electrode having a corresponding select signal input thereto; and
a precharge circuit including having a precharge transistor having a first main electrode connected to the corresponding one of the bit lines and an other main electrode connected to a second power line, and a precharge control circuit for causing the precharge transistor to turn on only when the corresponding select signal represents non-selection and a difference between a potential on the corresponding one of the bit lines and a potential on the second power line is greater than a predetermined value.
3. A semiconductor storage device according to claim 2 , wherein the precharge transistor has a same conductivity type as the select transistor, and the precharge control circuit is a NAND gate that supplies to the precharge transistor an output responsive to an inversion of a potential on the corresponding one of the bit lines and the corresponding select signal.
4. A semiconductor storage device according to claim 2 , wherein the precharge transistor has a conductivity type opposite to a conductivity type of the select transistor, and the precharge control circuit is a NOR gate that supplies to the precharge transistor an output responsive to a potential on the corresponding one of the bit lines and the corresponding select signal.
5. A semiconductor storage device according to claim 1 , wherein the first power line receives a ground potential and the second power line receives a power source potential.
6. A semiconductor storage device according to claim 1 , wherein the select transistor is an nMOS transistor and the precharge transistor is a pMOS transistor.
7. A semiconductor storage device according to claim 1 , wherein the select transistor is a pMOS transistor and the precharge transistor is an nMOS transistor.
8. A semiconductor storage device according to claim 2 , wherein the first power line receives a ground potential and the second power line receives a power source potential.
9. A semiconductor storage device according to claim 8 , wherein said predetermined value is a value corresponding to a half of said power source potential.
10. A semiconductor storage device according to claim 3 , wherein said precharge transistor is a pMOS transistor.
11. A semiconductor storage device according to claim 4 , wherein said precharge transistor is an nMOS transistor.