Methods and apparatus for high-speed serialized data transfer over network infrastructure using a different protocol

1. A method of transmitting data across a high-speed serial bus, the method comprising:

in accordance with a first TX symbol clock:

generating a 10-bit symbol on an IEEE 1394-compliant PHY having a port interface;

placing the generated 10-bit symbol on the port interface;

scrambling the 10-bit symbol;

encoding the 10-bit symbol; and

placing the 10-bit symbol in a FIFO;

in accordance with a second TX clock, the second TX clock running at a different speed than the first TX clock:

only on four out of every five TX clock cycles associated with the second clock, removing the 10-bit symbol from the FIFO;

deriving an 8-bit byte from the removed 10-bit symbol; and

sending the 8-bit byte to an IEEE 802.3-compliant PHY.

2. The method of claim 1 , wherein a null 10-bit symbol is placed in the FIFO if there are no 10-bit symbols present in the FIFO.

3. The method of claim 1 , wherein the 8-bit byte is derived from the 10-bit symbol by using 8 bits from the extracted 10-bit symbol, and the two remaining bits are stored.

4. The method of claim 3 , wherein a second 8-bit byte is derived by extracting from the FIFO a second 10-bit symbol and assembling an 8-bit byte from the stored two bits and six bits from the extracted second 10-bit symbol; the four remaining bits from the extracted second symbol are stored; and the second 8-bit byte is sent to the IEEE 802.3-compliant PHY.

5. The method of claim 4 , wherein a third 8-bit byte is derived by extracting from the FIFO a third 10-bit symbol and assembling an 8-bit byte from the four stored bits and four bits from the third extracted symbol; the six remaining bits from the extracted third symbol are stored; and the third 8-bit byte is sent to the IEEE 802.3-compliant PHY.

6. The method of claim 5 , wherein a fourth 8-bit byte is derived by extracting from the FIFO a fourth 10-bit symbol, and assembling an 8-bit byte from the six stored bits and 2 bits from the extracted fourth 10-bit symbol; the eight remaining bits from the extracted fourth symbol are stored; and the fourth 8-bit byte is sent to the IEEE 802.3-compliant PHY.

7. The method of claim 6 , wherein a fifth 8-bit byte is derived from the stored eight remaining bits and sent to the IEEE 802.3-compliant PHY.

8. The method of claim 1 , further comprising, in accordance with a phase amplitude modulation clock, sending the received 8-bit byte from the IEEE 802.3-compliant PHY to a device in accordance with a phase amplitude modulation clock.

9. A method of transmitting data across a high-speed serial bus, the method comprising:

in accordance with a first TX symbol clock:

generating a 10-bit symbol on an IEEE 1394-compliant PHY having a port interface;

placing the generated 10-bit symbol on the port interface;

performing flagged encoding the 10-bit symbol; and

placing the 10-bit symbol in a FIFO;

in accordance with a second TX clock, the second TX clock running at a different speed than the first TX clock:

only on four out of every five TX clock cycles associated with the second clock, removing the 10-bit symbol from the FIFO;

deriving an 8-bit byte from the removed 10-bit symbol; and

sending the 8-bit byte to an IEEE 802.3-compliant PHY.

10. The method of claim 9 , wherein a null 10-bit symbol is placed in the FIFO if there are no 10-bit symbols present in the FIFO.

11. The method of claim 9 , wherein the 8-bit byte is derived from the 10-bit symbol by using 8 bits from the extracted 10-bit symbol, and the two remaining bits are stored.

12. The method of claim 11 , wherein a second 8-bit byte is derived by extracting from the FIFO a second 10-bit symbol and assembling an 8-bit byte from the stored two bits and six bits from the extracted second 10-bit symbol; the four remaining bits from the extracted second symbol are stored; and the second 8-bit byte is sent to the IEEE 802.3-compliant PHY.

13. The method of claim 12 , wherein a third 8-bit byte is derived by extracting from the FIFO a third 10-bit symbol and assembling an 8-bit byte from the four stored bits and four bits from the third extracted symbol; the six remaining bits from the extracted third symbol are stored; and the third 8-bit byte is sent to the IEEE 802.3-compliant PHY.

14. The method of claim 13 , wherein a fourth 8-bit byte is derived by extracting from the FIFO a fourth 10-bit symbol, and assembling an 8-bit byte from the six stored bits and 2 bits from the extracted fourth 10-bit symbol; the eight remaining bits from the extracted fourth symbol are stored; and the fourth 8-bit byte is sent to the IEEE 802.3-compliant PHY.

15. The method of claim 14 , wherein a fifth 8-bit byte is derived from the stored eight remaining bits and sent to the IEEE 802.3-compliant PHY.

16. The method of claim 9 , further comprising, in accordance with a phase amplitude modulation clock, sending the received 8-bit byte from the IEEE 802.3-compliant PHY to a device in accordance with a phase amplitude modulation clock.

17. A method of transmitting data across a high-speed serial bus, the method comprising:

receiving an 8-bit byte on an 802.3-compliant PHY;

in accordance with a GMII RX clock:

if the received 8-bit byte contains a null symbol, then deleting the null symbol;

else if the received 8-bit byte does not contain a null symbol, then storing the 8-bit byte in a first register;

receiving a second 8-bit byte that does not contain a null symbol and storing the second 8-bit byte in a second register;

assembling a 10-bit symbol from the 8-bit byte stored in the first register and appending two bits from the 8-bit byte stored in the second register; and

placing the assembled 10-bit symbol in a first FIFO;

in accordance with a second clock:

removing the 10-bit symbol from the first FIFO;

performing 8B10B and control decoding on the removed 10-bit symbol; and

placing the decoded 10-bit symbol in a second FIFO;

in accordance with a third clock:

removing the decoded 10-bit symbol from the second FIFO; and

sending the decoded 10-bit symbol to an IEEE 1394-compliant PHY;

wherein the second clock is phase locked to the third clock, the frequency of null character deletion is used to control a phased locked loop, and the phase locked loop is associated with the second clock.

18. A method of transmitting data across a high-speed serial bus, the method comprising:

in accordance with a first clock:

generating a first multi-bit symbol on a first physical interface having a port only on fifty-eight out of every fifty-nine clock cycles associated with the first clock, wherein the multi-bit symbol is compliant with a first transmission protocol;

placing the generated first symbol on the port;

scrambling the first symbol;

encoding the scrambled first symbol;

placing the scrambled symbol in a buffer;

in accordance with a second clock running at a different speed than the first clock:

deriving a multi-bit byte from the scrambled symbol; and

sending the multi-bit byte to a second physical interface, the second interface utilizing a different communication protocol than the first interface.

19. The method of claim 18 , further comprising removing the scrambled symbol from the buffer before performing said act of deriving.

20. The method of claim 18 , further comprising placing a null multi-bit symbol in the buffer if there are no scrambled multi-bit symbols present in the buffer.

21. The method of claim 18 , wherein the multi-bit byte is derived by using 8 bits from the scrambled symbol.

22. The method of claim 18 , further comprising, in accordance with a phase amplitude modulation clock, sending the received multi-bit byte from the second interface to a device.

23. A method of transmitting data across a high-speed serial bus, the method comprising:

receiving an 8-bit byte on an 802.3-compliant PHY;

in accordance with a GMII RX clock:

if the received 8-bit byte contains a null symbol, then deleting the null symbol;

else if the received 8-bit byte does not contain a null symbol, then storing the 8-bit byte in a first register;

receiving a second 8-bit byte that does not contain a null symbol and storing the second 8-bit byte in a second register;

assembling a 10-bit symbol from the 8-bit byte stored in the first register and appending two bits from the 8-bit byte stored in the second register; and

placing the assembled 10-bit symbol in a first FIFO;

in accordance with a second clock:

removing the 10-bit symbol from the first FIFO;

performing 8B10B and control decoding on the removed 10-bit symbol; and

placing the decoded 10-bit symbol in a second FIFO;

in accordance with a third clock:

removing the decoded 10-bit symbol from the second FIFO; and

sending the decoded 10-bit symbol to an IEEE 1394-compliant PHY;

wherein the second clock is phase locked to the third clock; and

wherein frequency of null character deletion is used to control a phased locked loop, the phase locked loop associated with the second clock.

24. A method of transmitting data across a high-speed serial bus, the method comprising:

receiving an 8-bit byte on an 802.3-compliant PHY;

in accordance with a clock:

if the received 8-bit byte contains a null symbol, then deleting the null symbol;

else storing the 8-bit byte in a first location if it does not contain a null symbol, then;

receiving a second 8-bit byte that does not contain a null symbol and storing the second 8-bit byte in a second location;

assembling a 10-bit symbol from the 8-bit byte stored in the first location and appending two bits from the 8-bit byte stored in the second location; and

placing the assembled 10-bit symbol in a first buffer;

in accordance with a second clock:

removing the 10-bit symbol from the first buffer;

processing the removed 10-bit symbol to accomplish decoding thereof; and

placing the decoded 10-bit symbol in a second buffer;

in accordance with a third clock:

removing the decoded 10-bit symbol from the second buffer; and

sending the decoded 10-bit symbol to an IEEE 1394-compliant PHY;

wherein the second clock comprises a predetermined relationship to the third clock; and

wherein frequency of null character deletion is used to control a phased locked loop, the phase locked loop associated with the second clock.

25. A method of transmitting data across a high-speed serial bus, the method comprising:

receiving an 8-bit byte on an 802.3-compliant PHY;

in accordance with a GMII RX clock:

if the received 8-bit byte contains a null symbol, then deleting the null symbol;

else if the received 8-bit byte does not contain a null symbol, then storing the 8-bit byte in a first register;

receiving a second 8-bit byte that does not contain a null symbol and storing the second 8-bit byte in a second register;

assembling a 10-bit symbol from the 8-bit byte stored in the first register and appending two bits from the 8-bit byte stored in the second register; and

placing the assembled 10-bit symbol in a first FIFO;

in accordance with a second clock:

removing the 10-bit symbol from the first FIFO;

performing 8B10B and control decoding on the removed 10-bit symbol; and

placing the decoded 10-bit symbol in a second FIFO;

in accordance with a third clock:

removing the decoded 10-bit symbol from the second FIFO; and

sending the decoded 10-bit symbol to an IEEE 1394-compliant PHY;

wherein the second clock is phase locked to the third clock; and wherein the frequency of null character deletion is used to control a phased lock loop, the phase locked loop associated with the second clock.

26. A method of transmitting data across a high-speed serial bus, the method comprising:

in accordance with a first clock:

receiving a plurality of 8-bit bytes on an 802.3-compliant PHY;

deleting any null symbol appearing in any of the 8-bit bytes, wherein the frequency of null character deletion is used to control a phased locked loop associated with a second clock;

assembling a plurality of 10-bit symbols from the plurality of 8-bit bytes and from the contents of a register, wherein the register is adapted to store bits from an 8-bit byte that were not used in constructing a prior 10-bit symbol; and

placing the assembled 10-bit symbols in a first FIFO;

in accordance with the second clock:

removing the 10-bit symbols from the first FIFO,

decoding each removed 10-bit symbol; and

placing each decoded 10-bit symbol in a second FIFO; and

in accordance with a third clock:

removing each decoded 10-bit symbol from the second FIFO; and

sending each decoded 10-bit symbol to an IEEE 1394-compliant PHY.

27. A method of transmitting data across a high-speed serial bus, the method comprising:

receiving a first bit sequence on an 802.3-compliant PHY;

in accordance with a GMII RX clock:

if the first bit sequence does not contain a null symbol, then storing the first bit sequence;

else, if the first bit sequence contains a null symbol, then deleting the null symbol, wherein the frequency of null symbol deletion is used to control a phased locked loop associated with a second clock;

receiving a second bit sequence that does not contain a null symbol and storing the second bit sequence;

assembling a symbol based at least in part upon the first and second bit sequences; and

placing the symbol in a first FIFO data structure;

in accordance with a second clock:

removing the symbol from the first FIFO data structure;

decoding on the removed symbol; and

placing the decoded symbol in a second FIFO data structure; and

in accordance with a third clock:

removing the decoded symbol from the second FIFO; and

sending the decoded symbol to an IEEE 1394-compliant PHY.

28. A method of transmitting data across a serial bus, comprising:

in accordance with a first clock:

generating a first multi-bit symbol on a first physical interface only on n out of every m clock cycles associated with the first clock, n being an integer less than m, wherein the multi-bit symbol is compliant with a first transmission protocol;

placing the generated first symbol on the first interface;

scrambling the first symbol;

encoding the scrambled first symbol; and

placing the scrambled symbol in a buffer; and

in accordance with a second clock running at a different speed than the first clock:

deriving a multi-bit byte from the scrambled symbol; and

sending the multi-bit byte to a second physical interface, the second interface utilizing a different communication protocol than the first interface.

29. The method of claim 28 , further comprising removing the scrambled symbol from the buffer before performing said act of deriving.

30. The method of claim 28 , further comprising placing a null multi-bit symbol in the buffer if there are no scrambled multi-bit symbols present in the buffer.

31. The method of claim 28 , wherein the multi-bit byte is derived by using 8 bits from the scrambled symbol.

32. The method of claim 28 , further comprising, in accordance with a phase amplitude modulation clock, sending the received multi-bit byte from the second interface to a device.

33. The method of claim 28 , wherein n=58, and m=59.

34. A method of transmitting data across a serial bus, comprising:

in accordance with a first clock:

generating a first multi-bit symbol, the multi-bit symbol being compliant with a first transmission protocol;

placing the generated first symbol on the first interface;

scrambling and encoding the first symbol; and

placing the scrambled and encoded symbol in storage; and

in accordance with a second clock running at a different speed than the first clock:

deriving a multi-bit byte from the stored symbol;

sending the derived multi-bit byte to a second physical interface, the second interface utilizing a different communication protocol than the first interface; and

inserting at least one illegal symbol into a datastream carrying said multi-bit symbol, and utilizing a relationship between said illegal symbol and said multi-bit symbol to determine the validity of said multi-bit symbol.

35. The method of claim 34 , wherein said relationship between said illegal symbol and said multi-bit symbol comprises said multi-bit symbol immediately following said illegal symbol within said data stream.

36. A method of transmitting data across a serial bus, comprising:

in accordance with a first clock:

generating a first multi-bit symbol, the multi-bit symbol being compliant with a first transmission protocol;

placing the generated first symbol on the first interface;

scrambling and encoding the first symbol; and

placing the scrambled and encoded symbol in storage; and

in accordance with a second clock running at a different speed than the first clock:

deriving a multi-bit byte from the stored symbol; and

sending the derived multi-bit byte to a second physical interface, the second interface utilizing a different communication protocol than the first interface;

wherein said act of generating is only performed on a subset of the cycles associated with the first clock.