Performance FIR filter

1. A single bit FIR filter comprising:

a shift register comprising an input adapted to receive a plurality of serial input bits, said input bits being a single bit wide; said shift register comprising a predetermined number of nodes; said input nodes separated into at least two sets of nodes; wherein

said plurality of input bits to shift down a length of said shift register;

a storage device having a plurality of memory locations, each said memory location having an address;

means for using bits in a first set of nodes to address one of said memory locations and receive first content;

means for using bits in a second set of nodes, after applying an address offset to the bits which is not applied against the bits in the first set of nodes, to address one of said memory locations and receive second content; and

an accumulator providing at an output an accumulation of the first and second contents of the memory locations that were addressed.

2. A single bit FIR filter for comprising:

a register having an input for receiving a stream of serial input bits, said register comprising a plurality of node sets, each said node set outputting a set of input bits from said serial stream of input bits;

a memory comprising a plurality of memory locations each having an address and storing a value;

first circuitry for addressing the memory locations addressed by bits of a first one of said node sets to retrieve a first value and second circuitry for addressing the memory locations addressed by bits of a second one of said node sets, following application of an address offset to those bits of the second node set which has not been applied against the bits of the first node set, to retrieve a second value;

an accumulator adapted to receive the first and second values of said addressed memory locations; said accumulator adding said first and second values and producing a result; said result being substantially an output of said single bit FIR filter.

3. The single bit FIR filter of claim 2 , wherein each input node set comprises a same number of bits.

4. The single bit FIR filter of claim 2 , wherein said node sets comprise shift registers.

5. A method for providing a single bit FIR filter comprising:

receiving serial data into a register, said register being divided into first and second sets of data locations;

using data from said first set of data locations to address first memory locations;

applying an address offset to data from said second set of data locations to produce offset data, wherein the address offset is not applied against the data of the first set of data locations;

using the offset data to address second memory locations;

reading the contents of said addressed first and second memory locations;

accumulating the contents of said addressed first and second memory locations; and

providing a single bit FIR filter output comprising the accumulated contents.

6. The method of claim 5 further comprising, after said using step, shifting said data in the register at least one input data position.

7. The method of claim 5 further comprising shifting said data at least one data location in the register and after said step of providing repeating said method starting at said step of receiving.

8. The method of claim 5 further comprising loading said memory locations with values prior to the step of receiving.

9. The method of claim 5 , wherein each set of data locations comprises the same number of bits.

10. A method of providing a single bit FIR filter comprising:

inputting a serial stream of data into register having a plurality of data locations;

dividing said plurality of data locations into first and second sets of data locations;

addressing a memory location of a memory with data from the first set of data locations;

applying an address offset to data from said second set of data locations to produce offset data, wherein the address offset is not applied against the data of the first set of data locations;

addressing a memory location of the memory with the offset data;

reading the contents of each addressed memory location;

accumulating the read contents from the addressed memory locations; and

providing the accumulated contents as an FIR output.