Parallel operating system for uninterruptible power units

1. A system for operating in parallel a plurality of non-break power units inserted separately between (i) a bypass power source and a plurality of input power sources and (ii) a parallel bus,

each of said non-break power units comprising:

an inverter inserted between an input power source and the parallel bus; and

an AC switch inserted between the bypass power source and the parallel bus;

each of said non-break power units having:

an inverter power supply mode in which power is supplied from the input power source to the parallel bus by way of said inverter with said AC switch open; and

a bypass power supply mode in which, when operation of said inverter stops, said AC switch is closed to enable the AC power to be supplied directly to said parallel bus from said bypass power source by way of said AC switch,

each of said non-break power units further comprising:

a sequence control circuit for generating an output signal corresponding to an inverter power supply signal;

a switching element for outputting the inverter power supply signal based on the output signal of said sequence control circuit; and

a switch driving circuit for generating a driving signal for said AC switch in response to the inverter power supply signal, wherein

output terminals of said switching elements incorporated in said plurality of non-break power units, respectively, are connected in parallel with one another, and

said switch driving circuit incorporated in each of said non-break power units generates the driving signal for the associated AC switch based on a composite signal generated by synthesizing the inverter power supply signals in said non-break power units.

2. The non-break power unit parallel operating system according to claim 1 , wherein the output terminals of said switching elements incorporated in said non-break power units are connected in parallel with one another in a loop-like form.

3. The non-break power unit parallel operating system according to claim 1 , wherein each of said non-break power units further comprises:

a switch inserted on an output side of said non-break power unit, and

an auxiliary contact of said switch inserted on an input terminal side of said switching element of said non-break power unit, and said switching element outputs the inverter power supply signal by additionally taking into account a state signal of said switch of said non-break power unit to which said switching element belongs, as a condition for enabling the inverter power supply signal to be output.

4. The non-break power unit parallel operating system according to claim 3 , wherein said switch driving circuit of each of said non-break power units outputs a driving signal for said AC switch by additionally taking into account the state signal of said switch of said non-break power unit to which said switch driving circuit belongs, as a condition for enabling the driving signal to be output.

5. The non-break power unit parallel operating system according to claim 1 , wherein

each of said non-break power units further comprises an inverter power supply state detecting circuit inserted between the output terminal of said switching element and said switch driving circuit,

said inverter power supply state detecting circuit comprises:

a photo-coupler connected to the output terminal of said switching element, and

a diode connected in series to said photo-coupler, wherein the composite signal derived from synthesizing the inverter power supply signals is detected by said photo-coupler and said diode.

6. The non-break power unit parallel operating system according to claim 1 , wherein

each of said non-break power units further comprises a synchronous/asynchronous state detecting circuit for detecting synchronous/asynchronous state between the output voltage of said inverter and that of said bypass power source to output a synchronous state signal, and

said switch driving circuit outputs a driving signal for said AC switch by additionally taking into account the synchronous state signal in said non-break power unit to which said switch driving circuit belongs, as condition for enabling the driving signal to be output.

7. The non-break power unit parallel operating system according to claim 6 , wherein

the synchronous state signal containing an asynchronism signal indicates an asynchronous state between the output voltage of said inverter and the voltage of said bypass power source, and

an output terminal for the asynchronism signal is connected in parallel to the output terminal for the asynchronism signal of the other non-break power unit.

8. The non-break power unit parallel operating system according to claim 6 , wherein

the synchronous state signal contains a synchronism signal indicating a synchronous state between the output voltage of said inverter and the voltage of said bypass power source, and

an output terminal for the synchronism signal is connected in parallel to the output terminal for the synchronism signal of the other non-break power unit.

9. The non-break power unit parallel operating system according to claim 6 , wherein each of said non break power units further comprises:

a delay circuit for delaying the output signal of said sequence control circuit for a predetermined time;

an AND circuit for determining a logical product of the synchronous state signal and the output signal of said delay circuit; and

an OR circuit for determining a logical sum of the output signal of said AND circuit and the output signal of said sequence control circuit, wherein a logical sum signal output from said OR circuit is input to said switching element.