Polysilicon thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.
1. A thin film transistor array panel comprising:
an insulating substrate including a plurality of pixel areas;
a gate wire formed on the substrate;
a first data wire insulated from the gate wire and intersecting the gate wire to define the pixel areas;
a second data wire insulated from the gate wire and intersecting the gate wire;
a plurality of pixel electrodes formed in the pixel areas;
a plurality of switching thin film transistors connected to the gate wire and the data wire and including polysilicon members; and
a plurality of driving thin film transistors connected to the switching thin film transistors, the pixel electrodes, and the second data wire and including polysilicon members,
wherein the substrate includes a plurality of groups of divisional areas, each divisional area provided with the switching thin film transistors and the driving thin film transistors having substantially the same driving capacity, the switching thin film transistors and the driving thin film transistors in the divisional areas in one of the groups have different driving capacities, and the divisional areas in the different groups are mixed.
2. The thin film transistor array panel of claim 1 , wherein nearest neighbors of the divisional areas belong to the different groups, and next nearest neighbors of the divisional areas belong to the same group.
3. The thin film transistor array panel of claim 1 , wherein each pixel area includes one of the divisional areas.
4. The thin film transistor array panel of claim 1 , wherein the polysilicon members of the switching thin film transistors and the driving thin film transistors having different driving capacities have different crystalline characteristics.
5. A thin film transistor array panel comprising:
an insulating substrate including a plurality of pixel areas;
a plurality of polysilicon members provided on the pixel areas;
a gate insulating layer formed on the polysilicon members;
a gate wire formed on the gate insulating layer;
a first interlayer insulating layer formed on the gate wire;
a data wire formed on the first interlayer insulating layer and intersecting the gate wire to define the pixel areas;
a second interlayer insulating layer formed on the data wire; and
a plurality of pixel electrodes formed on the second interlayer insulating layer and disposed in the pixel areas,
wherein the substrate includes a plurality of groups of divisional areas, each divisional area provided with the polysilicon members having substantially the same driving capacity, the polysilicon members in the divisional areas in one of the groups have different driving capacities, and the divisional areas in the different groups are mixed.
6. The thin film transistor array panel of claim 5 , further comprising:
a plurality of organic light emitting members formed on the pixel electrodes;
a plurality of partitions formed on the pixel electrodes and defining areas occupied by the light emitting members; and
a common electrode formed on the light emitting members and the partitions.
7. The thin film transistor array panel of claim 5 , wherein the polysilicon members comprises a plurality of switching transistor portions including channel regions and source and drain regions, a plurality of driving transistor portions including channel regions and source and drain regions, and a plurality of storage electrode portions connected to the driving transistor portions;
the gate wire comprises a plurality of first gate electrodes, a plurality of second gate electrodes, and a plurality of storage electrodes overlapping the switching transistor portions, the driving transistor portions, and the storage electrode portions, respectively;
wherein the data wire comprises a plurality of first and second data lines, a plurality of first source electrodes connected to the first data lines and the source regions of the switching transistor portions, a plurality of first drain electrodes connected to the drain regions of the switching transistor portions and the second gate electrodes, and a plurality of second source electrodes connected to the second data lines and the source regions of the driving transistor portions; and
the pixel electrodes are connected to the drain regions of the driving transistor portions.