Multi-level boot hierarchy for software development on an integrated circuit
View Patent ↗A method of enabling software development for an integrated circuit, the integrated circuit being configured to run a boot program that prevents unverified software from subsequently being loaded onto, or run by, the integrated circuit, the method including the step of loading an intermediate program onto the integrated circuit, the intermediate program being customized for a particular one or more of a plurality of potential integrated circuits that, when run on the processor, enables loading or running of code on only the particular one or more integrated circuits.
1. An integrated circuit configured to:
run a boot program that verifies programs before said programs can be loaded onto, or run by, the integrated circuit by verifying whether said programs are signed with a boot key;
verify, with the boot program, a developmental boot program signed with the boot key which verifies developmental programs before said developmental programs can be loaded onto, or run by, the integrated circuit by verifying whether the integrated circuit has a predetermined integrated circuit identifier; and
load the verified developmental boot program and run the loaded developmental booth program thereby enabling loading or running of said developmental programs on the integrated circuit if the integrated circuit has the predetermined integrated circuit identifier, and
programmed with program code configured to:
receive software data and a digital signature of the software data
generate a first digest from the software data; and
compare the first digest against a second digest obtained via the digital signature that accompanied the received software data,
wherein the program is considered valid when the first and second digests match.
2. An integrated circuit according to claim 1 , wherein one or both of the digests were generated using a SHA1 function.
3. An integrated circuit according to claim 1 , wherein the boot program contains a plurality of keys, and one of the keys is selected for use in generating the first digest, the key being selected in accordance with a selection criterion.
4. An integrated circuit according to claim 3 , wherein the selection criterion is time-based, a particular one of the keys being selected depending on the time the selection is made.
5. An integrated circuit according to claim 3 , wherein the selection criteria relates to a physical arrangement or configuration of the integrated circuit.
6. An integrated circuit according to claim 5 , wherein the physical arrangement or configuration includes one or more of the following:
one or more pads wired to a reference voltage or to ground;
one or more fuses, one or more of which has been blown; or
the contents of non-volatile memory.