Dual edge count programmable frequency divider
View Patent ↗A frequency divider having an input frequency divider, an edge counter, and an output generator. The input frequency divider generates an intermediate signal having a frequency of f i from an input signal having a frequency f in , wherein f in =2f i . The edge counter generates a value equal to the number of edges in the intermediate signal that have occurred since a reset signal was generated. The output generator generates an output signal when the edge counter value reaches a value Q and generates the reset signal. In one embodiment, the edge counter includes a positive edge counter that counts the number of positive going transitions in the intermediate signal since the reset signal, a negative edge counter that counts the number of negative going transitions in the intermediate signal, and an adder that generates the sum of the positive and negative count values.
1. A frequency divider comprising:
an input frequency divider for generating an intermediate signal having a frequency of f i from an input signal having a frequency f in , wherein f in =Rf I , R being an integer >1;
an edge counter that generates a value equal to the sum of the number of positive edges and the number of negative edges in said intermediate signal that have occurred since a reset signal was generated; and
an output generator that generates an output signal when said edge counter value reaches a value Q and generates said reset signal.
2. The frequency divider of claim 1 wherein said output generator further comprises a port for receiving a signal specifying Q.
3. A frequency divider comprising:
an input frequency divider for generating an intermediate signal having a frequency of f i from an input signal having a frequency f in , wherein f in =Rf I ;
an edge counter that generates a value equal to the sum of the number of positive edges and the number of negative edges in said intermediate signal that have occurred since a reset signal was generated; and
an output generator that generates an output signal when said edge counter value reaches a value Q and generates said reset signal, wherein R=2.
4. A frequency divider comprising:
an input frequency divider for generating an intermediate signal having a frequency of f i from an input signal having a frequency f in , wherein f in =Rf I , R being an integer >1;
an edge counter that generates a value equal to the number of edges in said intermediate signal that have occurred since a reset signal was generated; and
an output generator that generates an output signal when said edge counter value reaches a value Q and generates said reset signal;
wherein said edge counter comprises a positive edge counter that generates a positive count value equal to the number of positive going transitions in said intermediate signal since said reset signal; a negative edge counter that generates a negative count value equal to the number of negative going transitions in said intermediate signal since said reset signal; and an adder that generates the sum of said positive count and said negative count.