Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
1. A thin film transistor array panel comprising:
a gate line formed on an insulating substrate;
a gate insulating layer on the gate line;
a semiconductor layer on the gate insulating layer;
a data line formed on the gate insulating layer and including a source electrode;
a drain electrode formed at least in part on the semiconductor layer;
a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part and a portion of an upper surface of the gate insulating layer; and
a pixel electrode formed on the passivation layer and contacting the drain electrode and the exposed portion of the gate insulating layer through the first contact hole.
2. The thin film transistor array panel of claim 1 , wherein at least one of the gate line, the data line, and the drain electrode comprises a lower film of Cr, Mo, or Mo alloy and an upper film of Al or Al alloy.
3. The thin film transistor array panel of claim 1 , wherein the gate insulating layer comprises silicon nitride and the passivation layer comprises silicon nitride.
4. The thin film transistor array panel of claim 1 , wherein the pixel electrode comprises IZO.
5. The thin film transistor array panel of claim 1 , wherein the passivation layer has second and third contact holes exposing end portions of the gate line and the data line, and the thin film transistor array panel further comprises contact assistants contacting the exposed end portions of the gate line and the data line.
6. A thin film transistor array panel comprising:
a gate line formed on an insulating substrate;
a gate insulating layer on the gate line;
a semiconductor layer on the gate insulating layer,
a data line formed on the gate insulating layer and including a source electrode;
a drain electrode formed at least in part on the semiconductor layer;
a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part and a portion of the gate insulating layer; and
a pixel electrode formed on the passivation layer and contacting the drain electrode and the exposed portion of the gate insulating layer through the first contact hole, wherein the pixel electrode contacts an upper surface of the gate insulating layer.
7. The thin film transistor array panel of claim 6 , wherein at least one of the gate line, the data line, and the drain electrode comprises a lower film of Cr, Mo, or Mo alloy and an upper film of Al or Al alloy.
8. The thin film transistor array panel of claim 6 , wherein the gate insulating layer comprises silicon nitride and the passivation layer comprises silicon nitride.
9. The thin film transistor array panel of claim 6 , wherein the pixel electrode comprises IZO.
10. The thin film transistor array panel of claim 6 , wherein the passivation layer has second and third contact holes exposing end portions of the gate line and the data line, and the thin film transistor array panel further comprises contact assistants contacting the exposed end portions of the gate line and the data line.