Physical layers
View Patent ↗Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.
1. A CMOS circuit comprising:
a first gate reference voltage;
a first bias circuit source; and
a device for adjusting a current from the first bias current source to a first circuit to reduce the variation of the first circuit as a function of process, voltage and temperature, the device including:
a first transistor having a gate, a first node and a second node, the gate of the first transistor being coupled to the first gate reference voltage, the first node of the first transistor being coupled to the first bias current source, the first transistor for generating a current sensitive to process, voltage and temperature variations;
a second transistor coupled to the first circuit and having a gate, a first node and a second node, the gate and the first node of the second transistor being coupled to the first node of the first transistor and the first bias current source, the second transistor for adjusting a current proportional to the difference between the current generated by the first bias current source and the current from the first transistor thereby compensating the current of the first bias current source for the process, voltage and temperature variations.
2. A CMOS circuit as claimed in claim 1 , wherein the structure of the gate of the first transistor includes a plurality of stripes.
3. A CMOS circuit as claimed in claim 1 , wherein the first transistor and the second transistor are NMOS transistors, the first node of the first transistor being a drain, the first node of the second transistor being a drain.
4. A CMOS circuit as claimed in claim 1 , wherein the first circuit includes at least one of a delay cell, a delay lock loop (DLL), a phase lock loop (PLL), a charge pump, an Operational Amplifier, and an Input/Output pad.