Semiconductor device and process of fabricating same
View Patent ↗A semiconductor device is provided with a FET having a sufficiently small short channel effect and sufficiently small junction capacitance and junction leakage current. The FET includes a channel region formed in a silicon substrate, a gate electrode formed on the channel region through the intermediary of a gate insulting film, heavily doped regions, and pocket regions. The pocket regions are formed to extend from inside the heavily doped regions, respectively, over inside the channel region. Because a pocket sub-region inside the respective heavily doped regions is formed to be located in regions shallower than the respective lower end faces of the heavily doped regions, junction capacitance and junction leakage current are reduced. Further, because respective pocket sub-regions inside the channel region are formed in regions deeper than the respective pocket sub-regions inside the heavily doped regions, a short channel effect can be reduced.
1. A process of fabricating a semiconductor device comprising:
forming a semiconductor substrate of a first conductivity type, the semiconductor substrate having a surface;
forming a gate oxide film and a gate electrode on the surface of the semiconductor substrate;
forming a sidewall on both sides of the gate electrode;
forming a surface covering film on exposed portions of the surface of the semiconductor substrate;
forming a source and a drain beneath the surface covering film by introducing a dopant of a second conductivity type into the semiconductor substrate through the surface covering film, wherein the source and the drain have a first depth from the surface of the semiconductor substrate;
removing the sidewalls so as to expose the surface of the semiconductor substrate near the gate electrode; and
forming a source side impurity layer and a drain side impurity layer by introducing a dopant of the first conductivity type into the semiconductor substrate through the surface covering film and into the exposed surface of the semiconductor substrate near the gate electrode,
wherein the source side impurity layer extends from inside the source at a second depth that is shallower than the first depth, to directly underneath the gate electrode at a third depth that is equal to or deeper than the first depth, and
wherein the drain side impurity layer extends from the drain at the second depth to directly underneath the gate electrode at the third depth.
2. A process of fabricating a semiconductor device according to claim 1 , further comprising forming LDD regions of the second conductivity type, in a vicinity of the gate electrode, and in respective regions directly above the source side impurity layer and the drain side impurity layer.
3. A process of fabricating a semiconductor device according to claim 2 , further comprising forming second sidewalls covering both sides of the gate oxide film and the gate electrode, respectively, on top of the LDD regions.
4. A process of fabricating a semiconductor device according to claim 1 , wherein said forming a source side impurity layer and a drain side impurity layer is conducted by an oblique ion implantation, so that the source side impurity layer and the drain side impurity layer extend up to regions directly underneath the gate electrode, respectively.
5. A process of fabricating a semiconductor device according to claim 1 , wherein the surface covering film is formed by oxidizing the surface of the semiconductor substrate.
6. A process of fabricating a semiconductor device according to claim 4 , wherein an angle of the oblique ion implantation is in a range of about 30 to 40 degrees.