Layout technique for address signal lines in decoders including stitched blocks
View Patent ↗A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.
1. A method comprising:
patterning a pixel section of an image sensor including pixel features having a first pitch on a surface; and
patterning a decoder section of the image sensor including features having a second pitch which is smaller than the first pitch on the surface, wherein said features include routing lines,
wherein a ratio of the second pitch to the first pitch is less than approximately 0.98; and
wherein the first pitch is approximately 9 μm and the second pitch is approximately 8.75 μm.
2. A method comprising:
patterning a pixel section of an image sensor including pixel features having a first pitch on a surface; and
patterning a decoder section of the image sensor including features having a second pitch which is smaller than the first pitch on the surface, wherein said features include routing lines,
wherein a ratio of the second pitch to the first pitch is less than approximately 0.95, and wherein the first pitch is approximately 18 μm and the second pitch is approximately 17 μm.