Multi-queue single-FIFO architecture for quality of service oriented systems
A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.
1. A multi-queue network apparatus for quality of service oriented communication, comprising: a host system comprising a system memory and a peripheral bus, the system memory including a plurality of queues each of which is configured to store data packets to be transmitted; and a peripheral module comprising: an arbiter, adapted to interface with the peripheral bus, maintaining a plurality of next access pointers targeting each queue within the system memory, respectively, determining which queue is to be serviced next contingent upon a quality of service policy, and fetching at least one data packet identified by the chosen queue's next access pointer; a data path controller, connected to the arbiter, accepting therefrom the fetched data packet; and two FIFO buffers, connected in parallel to the data path controller, storing and managing the fetched data packet in a first-in-first-out manner; wherein the data path controller allows one of the FIFO buffers to be filled with the fetched data packet while the other FIFO buffer is engaged in outgoing transference.
2. The multi-queue network apparatus of claim 1 wherein the host system maintains a plurality of lists of descriptors targeting each queues within the system memory, respectively, each list of descriptors includes access information for the data packets stored in an associated queue, and each descriptor is responsible for identifying one data packet.
3. The multi-queue network apparatus of claim 2 wherein each next access pointer points to the descriptor subsequent to a previous descriptor within a list of descriptors for a queue, in which the previous descriptor identifies the data packet most recently fetched from the queue.
4. The multi-queue network apparatus of claim 1 wherein the peripheral module further comprises physical layer interface logic, connected to the two FIFO buffers, to prepare the data packet for transmission on a physical medium.