Ultra-shallow metal oxide surface channel MOS transistor
An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.
1. A method for fabricating an ultra-shallow surface channel MOS transistor, the method comprising:
forming CMOS source and drain regions, and an intervening well region with a surface;
depositing a surface channel on the surface overlying the well region;
forming a high-k dielectric overlying the surface channel;
depositing a placeholder material overlying the surface channel;
conformally depositing oxide;
etching the placeholder material to form a gate region overlying the surface channel; and,
forming a gate electrode overlying the high-k dielectric in the gate region.
2. The method of claim 1 further comprising:
following the deposition of the placeholder material, lightly doped drain (LDD) processing the source and drain regions;
wherein forming a high-k dielectric insulator overlying the surface channel includes depositing the high-k dielectric prior to the deposition of the placeholder material;
the method further comprising:
forming sidewall insulators adjacent the surface channel, high-k dielectric insulator, and gate region; and,
heavy ion implanting and activating the source and drain regions.
3. The method of claim 2 wherein forming sidewall insulators adjacent the surface channel, high-k dielectric insulator, and gate region includes forming sidewalls from a material selected from the group including Si3N4 and Al2O3.
4. The method of claim 1 further comprising:
prior to the deposition of the surface channel, lightly doped drain (LDD) processing the source and drain regions;
heavy ion implanting and activating the source and drain regions; and,
wherein forming a high-k dielectric insulator overlying the surface channel includes depositing the high-k dielectric following the etching of the placeholder material to form the gate region.
5. The method of claim 1 wherein depositing a placeholder material overlying the surface channel includes forming placeholder material to a first thickness with a placeholder material surface; and,
wherein conformally depositing oxide includes depositing oxide to a second thickness in the range of 1.2 to 1.5 times the first thickness; and,
the method further comprising:
chemical mechanical polishing (CMP) the oxide to the level of the placeholder material surface.
6. A method for fabricating an ultra-shallow surface channel MOS transistor, the method comprising:
forming CMOS source and drain regions, and an intervening well region with a surface;
depositing a metal oxide surface channel on the surface overlying the well region having a thickness in the range in the range of 10 to 20 nanometers (nm);
forming a high-k dielectric overlying the surface channel; and,
forming a gate electrode overlying the high-k dielectric.
7. A method for fabricating an ultra-shallow surface channel MOS transistor, the method comprising:
forming CMOS source and drain regions, and an intervening well region with a surface;
depositing a metal oxide surface channel on the surface overlying the well region having a resistivity in the range between 0.1 and 1000 ohm-cm;
forming a high-k dielectric overlying the surface channel; and,
forming a gate electrode overlying the high-k dielectric.
8. An ultra-shallow surface channel MOS transistor, the transistor comprising:
a source region;
a drain region;
a well region intervening between the source and drain with a surface;
a surface channel overlying the well region;
a high-k dielectric insulator overlying the surface channel;
a placeholder overlying the surface channel, forming a temporary gate region; and,
a gate electrode overlying the high-k dielectric layer, formed in the gate region.
9. The transistor of claim 8 wherein the placeholder is temporarily formed directly overlying the high-k dielectric insulator;
the transistor further comprising:
sidewall insulators adjacent the surface channel, high-k dielectric insulator, and the gate region.
10. The transistor of claim 9 wherein the sidewall insulators are a material selected from the group including Si 3 N 4 and Al 2 O 3 .
11. The transistor of claim 8 wherein the placeholder is temporarily formed directly overlying the surface channel.
12. An ultra-shallow surface channel MOS transistor, the transistor comprising:
a source region;
a drain region;
a well region intervening between the source and drain with a surface;
a metal oxide surface channel overlying the well region having a thickness in the range in the range of 10 to 20 nanometers (nm);
a high-k dielectric insulator overlying the surface channel; and
a gate electrode overlying the high-k dielectric layer.
13. An ultra-shallow surface channel MOS transistor, the transistor comprising:
a source region;
a drain region;
a well region intervening between the source and drain with a surface;
a metal oxide surface channel overlying the well region having a resistivity in the range between 0.1 and 1000 ohm-cm;
a high-k dielectric insulator overlying the surface channel; and
a gate electrode overlying the high-k dielectric layer.