High-speed, current driven latch
View Patent ↗A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
1. A method of changing the output of a latch circuit, the output having a first state and a second state, the latch circuit comprising a SET transistor and a RESET transistor, the method comprising;
at the first state, conducting a first current in a first latch transistor and a SET transistor, said first latch transistor having a base coupled by a resistive element to the base of the SET transistor, and using a portion of the first current to bias the SET transistor at an operational point lower than a first threshold;
at the second state, conducting the first current in a second latch transistor and a RESET transistor, said second latch transistor having a base coupled by a resistive element to the base of the RESET transistor, and using a portion of the first current to bias the RESET transistor at an operational point lower than a second threshold;
to vary the output from the first state to the second state, providing a second current that raises the base of the SET transistor to the first threshold; and
to vary the output from the second state to the first state, providing the second current that raises the base of the RESET transistor to the second threshold.
2. The method of claim 1 , the providing the first current comprising providing the first current from two substantially equal current sources.
3. The method of claim 2 , the providing the second current comprising causing a relatively small voltage change in the base of one of the SET and RESET transistors.
4. An oscillator that oscillates an output using the method of claim 1 .
5. The oscillator of claim 4 further comprising temperature compensating the oscillator.