Method and apparatus of adding grant information to a memory
View Patent ↗A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.
1. A method of adding grant information to a memory that stores information about a series of arbitration periods, the method comprising:
assigning a number of first addresses to a group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits; and
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period.
2. The method of claim 1 and further comprising for each second address, writing grant information to the memory about the corresponding device.
3. The method of claim 2 wherein each device is assigned only consecutive first addresses.
4. A method of adding grant information to a memory that stores information about a series of arbitration periods, the method comprising:
assigning a number of first addresses to a group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits, each device being assigned only consecutive first addresses, first addresses being assigned to a first device, and second addresses being formed for the first device before first addresses are assigned to a second device;
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period; and
for each second address, writing grant information to the memory about the corresponding device.
5. A method of adding grant information to a memory that stores information about a series of arbitration periods, the method comprising:
assigning a number of first addresses to a group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits; and
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period, the sequence of bits being rearranged by:
setting a least significant bit of a second address to have a value equal to a most significant bit in a first address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the first address.
6. The method of claim 5 and further comprising setting a second next to the least significant bit of the second address to have a value equal to a second next to the most significant bit in the first address.
7. A method of adding grant information to a memory that stores information about a series of arbitration periods, the method comprising:
assigning a number of first addresses to a group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits; and
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period, the sequence of bits being rearranged by:
gray encoding a first address to form an intermediate address;
setting a least significant bit of a second address to have a value equal to a most significant bit in the intermediate address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the intermediate address.
8. The method of claim 7 and further comprising setting a second next to the least significant bit of the second address to have a value equal to a second next to the most significant bit in the intermediate address.
9. A communications circuit comprising:
a transmit circuit that transmits information onto a bus;
a receive circuit that receives information from the bus;
a memory that stores information on a series of arbitration periods; and
a logic circuit connected to the transmit circuit, the receive circuit, and the memory, if grant information for a group of devices is to be added to the memory, the logic circuit assigns a number of first addresses to the group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits, the logic circuit forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period.
10. The communications circuit of claim 9 wherein the logic circuit forms the second addresses by:
gray encoding a first address to form an intermediate address;
setting a least significant bit of a second address to have a value equal to the most significant bit in the intermediate address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the intermediate address.
11. A communications circuit comprising:
a transmit circuit that transmits information onto a bus;
a receive circuit that receives information from the bus;
a memory that stores information on a series of arbitration periods; and
a logic circuit connected to the transmit circuit, the receive circuit, and the memory, if grant information for a group of devices is to be added to the memory, the logic circuit assigns a number of first addresses to the group of devices such that two or more consecutive first addresses are assigned to each device and no two devices have the same first addresses, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits, the logic circuit forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address and each second address has a corresponding device by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period, the logic circuit forming the second addresses by:
setting a least significant bit of a second address to have a value equal to the most significant bit in a first address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the first address.
12. A method of adding grant information to a memory that stores information about a series of arbitration periods, the method comprising:
assigning a number of first addresses to a device, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, each first address having a sequence of bits;
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address by rearranging the sequence of bits in a plurality of the number of first addresses, the first addresses and second addresses having an equal number of bits, each second address representing one arbitration period; and
storing information in the memory about the device at each location defined by a second address.
13. The method of claim 12 wherein the rearranging includes:
setting a least significant bit of a second address to have a value equal to a most significant bit in a first address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the first address.
14. The method of claim 13 wherein the rearranging further includes setting a second next to the least significant bit of the second address to have a value equal to a second next to the most significant bit in the first address.
15. The method of claim 12 wherein forming further includes:
gray encoding a first address to form an intermediate address;
setting a least significant bit of a second address to have a value equal to a most significant bit in the intermediate address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the intermediate address.
16. A method of adding grant information to a memory that stores information on a series of arbitration periods, the method comprising:
assigning a number of first addresses to a device, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, no two first addresses being identical, each first address having a sequence of bits; and
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period, no two second addresses being identical.
17. A method of adding grant information to a memory that stores information on a series of arbitration periods, the method comprising:
assigning a number of first addresses to a device, the number of first addresses representing a corresponding number of arbitration periods such that each first address represents one arbitration period, no two first addresses being identical, each first address having a sequence of bits;
forming a number of second addresses from the number of the first addresses such that each first address has a corresponding second address by rearranging the sequence of bits in a plurality of the number of first addresses, each second address representing one arbitration period, no two second addresses being identical; and
storing information in the memory about the device at each location defined by a second address.
18. The method of claim 17 wherein the rearranging includes:
setting a least significant bit of a second address to have a value equal to a most significant bit in a first address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the first address.
19. The method of claim 18 wherein the rearranging further includes setting a second next to the least significant bit of the second address to have a value equal to a second next to the most significant bit in the first address.
20. The method of claim 17 wherein forming further includes:
gray encoding a first address to form an intermediate address;
setting a least significant bit of a second address to have a value equal to a most significant bit in the intermediate address; and
setting a first next to the least significant bit of the second address to have a value equal to a first next to the most significant bit in the intermediate address.