Thin film transistor type display device, method of manufacturing thin film element, thin film transistor circuit board, electro-optical device, and electronic apparatus
View Patent ↗The invention reduces the size of an element chip and reduces the manufacturing cost in a thin film transistor type display device in which thin film transistors are formed on a first substrate, wiring lines are formed on a second substrate, and the element chip, including one or more thin film transistors, is peeled off from the first substrate and transferred to the second substrate. In the patterning process of the thin film transistors, holographic lithography or a dynamic auto focus system is used, a design rule of 1.0 μm or less is used, and only a polycrystalline silicon layer and a first metal layer are used as the wiring lines of the element chip.
1. A method of manufacturing a thin film transistor circuit substrate, comprising the steps of:
forming a plurality of element chips, each having at least one thin film transistor, on a first substrate via a peeling layer;
forming a wiring line on a second substrate;
pressingly attaching at least one element chip of the plurality of element chips in a predetermined position on the second substrate via an adhesive, and electrically connecting the at least one element chip and the wiring line; and
peeling the at least one element chip from the first substrate, by irradiating a laser beam onto the peeling layer, after electrically connecting the at least one element chip and the wiring line;
wherein the step of forming the thin film transistor includes the steps of forming an amorphous silicon layer on the peeling layer, crystallizing the amorphous silicon layer by irradiating a laser beam thereonto, and then forming a polycrystalline silicon layer by patterning the crystallized amorphous silicon layer, forming an insulating film on the first substrate and the polycrystalline silicon layer, and forming the gate metal on the insulating film, and then forming a gate electrode by patterning the gate metal; wherein
holographic lithography and a dynamic auto focus system are used for patterning the crystallized amorphous silicon layer and the gate metal;
stepper exposure is used for patterning other than patterning the crystallized amorphous silicon layer and the gate metal; and
a design rule finer than a design rule used for the other patterning is used for patterning the crystallized amorphous silicon layer and the gate metal.
2. The method according to claim 1 , further comprising using the design rule of 1.0 micron or less for the patterning of the crystallized amorphous silicon layer and the gate metal.
3. The method according to claim 1 , the other patterning including the patterning of the crystallized amorphous silicon layer.