Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon insertion of the dummy patterns which are different from an actual wiring pattern. The semiconductor device has a configuration wherein a gate wiring pattern is formed on a semiconductor substrate, a plurality of dummy patterns are provided therearound, and a BPSG oxide film which is flattened by CMP is formed on the gate wiring pattern and the dummy patterns as an interlayer insulating film. In the semiconductor device, the dummy patterns are formed so as to include pattern non-forming regions such as slits.
1. A semiconductor device comprising:
a semiconductor substrate having a pattern area and a non-pattern area;
a conductor pattern formed on said pattern area of said semiconductor substrate;
a plurality of dummy patterns formed on said non-pattern area of said semiconductor substrate;
an insulating film formed on said conductive pattern and said plurality of dummy patterns;
wherein said insulating film is formed by a chemical vapor deposition and is smoothed by chemical mechanical polishing;
wherein each of said plurality of dummy patterns are formed in a plurality of dummy areas, each of said plurality of dummy areas having a same shape, and each of said plurality of dummy patterns being arranged in a matrix with predetermined spacing;
wherein each of said dummy patterns has a space portion within each of the dummy areas so that a pattern ratio of said semiconductor device is reduced;
wherein each of said dummy patterns includes an opening at the space portion, the opening having a shape of a letter or a number, each opening of said dummy patterns having a width less than 72 μm; and
wherein the openings of the dummy patterns each have a shape different from one another.
2. A semiconductor device according to claim 1 , wherein each of said dummy patterns has a rectangular outline.
3. A semiconductor device according to claim 2 , wherein each opening has a shape of a plurality of letters.
4. A method of manufacturing the semiconductor device of claim 1 , the method comprising:
forming the conductor pattern and the dummy patterns above the semiconductor substrate;
forming the insulating film on the conductor pattern and the dummy patterns by chemical vapor deposition, the opening of each dummy pattern being filled by the insulating film; and
smoothing the insulating film by chemical mechanical polishing.
5. The method according to claim 4 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film.
6. The method according to claim 4 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film.