Thin film transistor substrate and its manufacture
View Patent ↗A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is formed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.
1. A thin film transistor substrate comprising:
a substrate;
a first transistor structure having a first semiconductor layer formed on said substrate, a first gate insulating film and a first gate electrode, wherein a channel region of said first semiconductor layer under said first gate electrode is intentionally doped with only p-type impurities, said first semiconductor layer includes n-type LDD regions outside the channel region and high impurity concentration n-type source/drain regions outside the n-type LDD regions, and said first gate electrode is made of a lamination of a first metal layer and a second metal layer;
a second transistor structure having a second semiconductor layer formed on said substrate, a second gate insulating film and a second gate electrode, wherein a channel region of said second semiconductor layer under said second gate electrode is intentionally doped with only p-type impurities, said second semiconductor layer includes high impurity concentration n-type source/drain regions outside the channel region, and said second gate electrode is made of a lamination of said first metal layer and said second metal layer; and
a third transistor structure having a third semiconductor layer formed on said substrate, a third gate insulating film and a third gate electrode, wherein a channel region of said third semiconductor layer under said third gate electrode is intentionally doped with p-type impurities and n-type impurities, said third semiconductor layer includes high impurity concentration p-type source/drain regions outside the channel region, and said third gate electrode is made of said second metal layer.
2. The thin film transistor substrate according to claim 1 , wherein said second semiconductor layer has n-type LDD regions outside the channel region, and the high impurity concentration n-type source/drain regions outside the n-type LDD regions.
3. The thin film transistor substrate according to claim 1 , wherein said first and second metal layers have different etching characteristics.
4. The thin film transistor substrate according to claim 3 , wherein said first metal layer is a refractory metal layer and said second metal layer is an aluminum alloy layer.
5. A thin film transistor substrate comprising:
a substrate;
a first transistor structure having a first semiconductor layer formed on said substrate, a first gate insulating film and a first gate electrode, wherein a channel region of said first semiconductor layer under said first gate electrode is intentionally doped with only p-type impurities, said first semiconductor layer includes n-type LDD regions outside the channel region and high impurity concentration n-type source/drain regions outside the n-type LDD regions, and said first gate electrode is made of a first metal layer;
a second transistor structure having a second semiconductor layer formed on said substrate, a second gate insulating film and a second gate electrode, wherein a channel region of said second semiconductor layer under said second gate electrode is intentionally doped with p-type impurities at the first impurity concentration, said second semiconductor layer includes high impurity concentration n-type source/drain regions outside the channel region, and said second gate electrode is made of said first metal layer; and
a third transistor structure having a third semiconductor layer formed on said substrate, a third gate insulating film and a third gate electrode, wherein a channel region of said third semiconductor layer under said third gate electrode is intentionally doped with p-type impurities at a second impurity concentration lower than the first impurity concentration, said third semiconductor layer includes high impurity concentration p-type source/drain regions outside the channel region, and said third gate electrode is made of a second metal layer that is different from said first metal layer.
6. The thin film transistor substrate according to claim 5 , wherein said second semiconductor layer has n-type LDD regions outside the channel region, and the high impurity concentration n-type source/drain regions outside the n-type LDD regions.
7. The thin film transistor substrate according to claim 5 , wherein said first metal layer has etching characteristics different from those of said second metal layer.
8. The thin film transistor substrate according to claim 7 , wherein said first metal layer is a refractory metal layer and said second metal layer is an aluminum alloy layer.