Methods and systems for detecting memory address transfer errors in an address bus
View Patent ↗A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequently, the data ECC check bits are written to a memory and the data ECC check bits enable detection of transfer errors in the address bus. A system for detecting transfer errors in an address bus is also described.
1. A method for detecting transfer errors in an address bus, comprising:
generating a first address parity using a memory address;
scrambling at least two data error-correction-code (ECC) check bits using the first address parity; and
writing the data ECC check bits to a memory, the data ECC check bits enabling detection of transfer errors in the address bus;
generating a second address parity using the memory address;
reading the data ECC check bits from the memory; and
unscrambling the at least two data ECC check bits using the second address parity, the data ECC check bits enabling detection of transfer errors in the address bus;
wherein the method operation of unscrambling the at least two data ECC check bits is selected from one of using an exclusive-OR function and using an exclusive-NOR function.
2. The method of claim 1 , further comprising:
executing an ECC operation; and
reporting an ECC error to an exception-handling software if the at least two data ECC check bits signal an error.
3. A method for detecting transfer errors in an address bus, comprising:
generating a first address parity using a memory address;
scrambling at least two data error-correction-code (ECC) check bits using the first address parity; and
writing the data ECC check bits to a memory, the data ECC check bits enabling detection of transfer errors in the address bus;
wherein the at least two data ECC check bits are selected from the group consisting of two most significant bits and two least significant bits.
4. A method for detecting transfer errors in an address bus, comprising:
generating a second address parity using a memory address;
reading data error-correction-code (ECC) check bits from the memory; and
unscrambling at least two previously scrambled data ECC check bits using the second address parity, the data ECC check bits enabling detection of transfer errors in the address bus;
executing an ECC operation; and
reporting an ECC error to an exception-handling software if the at least two previously scrambled data ECC check bits signal an error.
5. A method for detecting transfer errors in an address bus, comprising:
generating a second address parity using a memory address;
reading data error-correction-code (ECC) check bits from the memory; and
unscrambling at least two previously scrambled data ECC check bits using the second address parity, the data ECC check bits enabling detection of transfer errors in the address bus;
wherein the method operation of unscrambling the at least two previously scrambled data ECC check bits is selected from one of using an exclusive-OR function and using an exclusive-NOR function.
6. A method for detecting transfer errors in an address bus, comprising:
generating a second address parity using a memory address;
reading data error-correction-code (ECC) check bits from the memory; and
unscrambling at least two previously scrambled data ECC check bits using the second address parity, the data ECC check bits enabling detection of transfer errors in the address bus;
wherein the at least two previously scrambled data ECC check bits are selected from the group consisting of two most significant bits and two least significant bits.