IP Library Granted Patent US 7,038,438
Granted Patent B2
US 7,038,438 · App. 10/767,937 · Granted May 2, 2006

Controller for a power converter and a method of controlling a switch thereof

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Quick Facts
Patent No.
US 7,038,438
App. No.
10/767,937
Granted
May 2, 2006
Kind
B2
Abstract

A controller for, related method of controlling a switch of, a power converter and a power converter employing the same. The controller is employable with a power converter including a switch of a power train configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof. In one embodiment, the controller includes a sparse analog-to-digital converter configured to determine a difference between the output characteristic and a desired characteristic and provide an error signal representing the difference in discrete steps. A magnitude of the discrete steps is small when the difference is small and the magnitude of the discrete steps is larger when the difference is larger. The controller also includes a duty cycle processor configured to provide a digital duty cycle signal to control the duty cycle of the switch as a function of the error signal.

Claims (33)

1. A controller for use with a power train of a power converter including a switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof, comprising:

a sparse analog-to-digital converter configured to determine a difference between said output characteristic and a desired characteristic and provide an error signal representing said difference in discrete steps, a magnitude of said discrete steps being small when said difference is small and a magnitude of said discrete steps being larger when said difference is larger; and

a duty cycle processor configured to provide a digital duty cycle signal to control said duty cycle of said switch as a function of said error signal.

2. The controller as recited in claim 1 wherein said sparse analog-to-digital converter comprises a resistor divider configured to provide at least one scaled representation of said desired characteristic.

3. The controller as recited in claim 1 wherein said sparse analog-to-digital converter further comprises a comparator bank configured to provide said error signal.

4. The controller as recited in claim 1 wherein said duty cycle processor comprises a duty cycle encoder configured to provide a modification signal representing a change to said duty cycle as a function of said error signal.

5. The controller as recited in claim 4 wherein said duty cycle processor further comprises a duty cycle conditioning circuit configured to provide a conditioned modification signal as a function of said modification signal from said duty cycle encoder.

6. The controller as recited in claim 5 wherein said duty cycle processor further comprises a full adder and a duty cycle register configured to provide said digital duty cycle signal as a function of said conditioned modification signal from said duty cycle conditioning circuit.

7. The controller as recited in claim 1 further comprising a digital-to-analog converter configured to transform said desired characteristic from a digital format to an analog format employable by said sparse analog-to-digital converter.

8. The controller as recited in claim 1 further comprising a modulator configured to convert said digital duty cycle signal into a signal to control said duty cycle of said switch of said power converter.

9. A method of controlling a duty cycle of a switch to provide a regulated output characteristic at an output of a power converter, comprising:

determining a difference between said output characteristic and a desired characteristic and providing an error signal representing said difference in discrete steps, a magnitude of said discrete steps being small when said difference is small and a magnitude of said discrete steps being larger when said difference is larger; and

providing a digital duty cycle signal to control said duty cycle of said switch as a function of said error signal.

10. The method as recited in claim 9 wherein said determining comprises providing at least one scaled representation of said desired characteristic and providing said error signal therefrom.

11. The method as recited in claim 9 wherein said providing comprises providing a modification signal representing a change to said duty cycle as a function of said error signal.

12. The method as recited in claim 11 wherein said providing further comprises providing a conditioned modification signal as a function of said modification signal.

13. The method as recited in claim 12 wherein said providing further comprises modifying and storing contents of a duty cycle register to provide said digital duty cycle signal as a function of said conditioned modification signal.

14. The method as recited in claim 9 further comprising transforming said desired characteristic from a digital format to an analog format employable by said act of determining.

15. The method as recited in claim 9 further comprising converting said digital duty cycle signal into a drive signal for said switch of said power converter.

16. A power converter, comprising:

a power train including a switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output of said power converter; and

a controller, including:

a sparse analog-to-digital converter configured to determine a difference between said output characteristic and a desired characteristic and provide an error signal representing said difference in discrete steps, a magnitude of said discrete steps being small when said difference is small and a magnitude of said discrete steps being larger when said difference is larger, and

a duty cycle processor configured to provide a digital duty cycle signal to control said duty cycle of said switch as a function of said error signal.

17. The power converter as recited in claim 16 wherein said sparse analog-to-digital converter comprises:

a resistor divider configured to provide at least one scaled representation of said desired characteristic, and

a comparator bank configured to provide said error signal.

18. The power converter as recited in claim 16 wherein said duty cycle processor comprises:

a duty cycle encoder configured to provide a modification signal representing a change to said duty cycle as a function of said error signal,

a duty cycle conditioning circuit configured to provide a conditioned modification signal as a function of said modification signal from said duty cycle encoder, and

a full adder and a duty cycle register configured to provide said digital duty cycle signal as a function of said conditioned modification signal from said duty cycle conditioning circuit.

19. The power converter as recited in claim 16 wherein said controller further comprises a digital-to-analog converter configured to transform said desired characteristic from a digital format to an analog format employable by said sparse analog-to-digital converter.

20. The power converter as recited in claim 16 wherein said controller further comprises a modulator configured to convert said digital duty cycle signal into a signal employable by a driver to provide a drive signal to said switch of said power converter.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2022
From: ALTERA CORPORATION
To: INTEL CORPORATION
Reel/Frame 061159/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2022
From: ENPIRION, INC.
To: ALTERA CORPORATION
Reel/Frame 060390/0187 →
RELEASE OF SECURITY INTEREST Recorded Feb 20, 2009
From: HERCULES TECHNOLOGY II, L.P.
To: ENPIRION, INC.
Reel/Frame 022277/0935 →
SECURITY AGREEMENT Recorded May 27, 2008
From: ENPIRION, INC.
To: HERCULES TECHNOLOGY II, L.P.
Reel/Frame 021029/0674 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2004
From: DWARAKANATH, MIRMIRA RAMARAO; WANG, JUE; WESTON, HARRY THOMAS
To: ENPIRION, INC.
Reel/Frame 014856/0441 →