System and method for providing error check and correction in memory systems
View Patent ↗A system for providing error check and correction (ECC) is provided. The system includes an ECC interface for storing ECC codes in a first memory system and storing data in a second memory system. The ECC interface corrects errors in the data received from the second memory system utilizing the ECC codes received from the first memory system. The ECC interface asserts at least one error flag upon detecting errors in the data, and a processor monitors the at least one error flag and corrects the data stored in the first memory system.
1. A system that provides error checking and correction for data saved in storage media, comprising:
a synchronous storage medium that is utilized to store data and at least one associated data code; and
an interface component that reads the data and the at least one associated data code from the storage medium, compares the at least one associated data code with at least one calculated data code in order to detect data errors before providing the data to a processor, the interface facilitates correcting associated data errors by notifying a processor of a control system application of the data errors with at least an error flag so that the processor corrects errors during low priority operations without hindering system performance.
2. The system of claim 1 , the interface component further generates at least one data code for data to be written to the storage medium and writes the data and the at least one data code to the storage medium.
3. The system of claim 1 , the interface component further monitors and controls a device's access to the storage medium.
4. The system of claim 1 , the at least one error flag indicates that a data error is one of a single bit error, a plurality of single bit errors, and a multi-bit error.
5. The system of claim 1 , the at least one error flag is utilized in a statistical analysis to generate information that is employed to troubleshoot the system.
6. The system of claim 1 , the interface component further latches an address to error data in order to point to the most recent fault storage location in the storage medium.
7. The system of claim 1 , the storage medium is at least one of an array of memory locations and a plurality of memory devices.
8. The system of claim 1 , the data code is a 7-bit Hamming code.
9. The system of claim 1 , the interface component includes at least a storage medium controller, a bus interface, and error checking and correction logic.
10. The system of claim 9 , the storage medium controller includes Read-Modify-Write (RMW)logic.
11. A method that corrects data errors in memory devices utilized in an industrial environment, comprising:
retrieving requested data and at least one associated code from a synchronous memory system;
comparing the at least one retrieved code with at least one calculated code to detect data errors;
correcting the data errors prior to providing the requested data to a processor; and
notifying a processor of a control system application of the data errors with an error flag which enables the processor to correct errors after reading the data during low priority operations without hindering system performance.
12. The method of claim 11 , further comprising generating at least one data code for data that is to be written to the memory, and writing the data and the at least one generated data code to the memory.
13. The method of claim 11 , further comprising latching a memory address corresponding to data with errors to provide the most recent fault location.
14. The method of claim 11 , further comprising monitoring and controlling a device's access to the memory.
15. The system of claim 11 , the data and codes are retrieved and compared when at least one of the following occurs: a request to retrieve data is received, a predetermined interval lapses and an interrupt is received.
16. A system that corrects stored data errors, comprising
means for associating stored data in a synchronous memory system with data codes; and
means for detecting data errors via the data codes before providing the data to a processor;
means for indicating to the processor of a control system application at least one data error is detected; and
means for correcting the data error after providing corrected data to the processor for single bit errors.