IP Library Granted Patent US 7,279,257
Granted Patent B2
US 7,279,257 · App. 10/768,998 · Granted Oct 9, 2007

Pattern forming method, method of manufacturing thin film transistor substrate, method of manufacturing liquid crystal display and exposure mask

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Quick Facts
Patent No.
US 7,279,257
App. No.
10/768,998
Granted
Oct 9, 2007
Kind
B2
Abstract

The invention relates to a pattern forming method, a method of manufacturing a TFT substrate, a method of manufacturing a liquid crystal display and an exposure mask and provides a pattern forming method, a method of manufacturing a TFT substrate, a method of manufacturing a liquid crystal display and an exposure mask which make it possible to provide a liquid crystal display having high display characteristics. In a pattern forming method for forming a resist pattern extending across a first divided exposure region and a second divided exposure region among a plurality of divided exposure regions on a substrate, a resist film is formed on the substrate; the resist film in the first divided exposure region is exposed using an exposure mask to form a latent image which defines one edge of a resist pattern in the vicinity of a boundary between the first divided exposure region and the second divided exposure region; the resist film in the second divided exposure region is exposed using another exposure mask to form a latent image which defines another edge of the resist pattern in the vicinity of the boundary; and the resist film is developed to form the resist pattern.

Claims (27)

1. A pattern forming method for forming a resist pattern on a substrate having a plurality of divided exposure regions, the resist pattern extending across a first divided exposure region and a second divided exposure region among the plurality of divided exposure regions, the method comprising the steps of:

forming a resist film on the substrate;

exposing the resist film in the first divided exposure region to form a latent image which defines one edge of the resist pattern in the vicinity of a boundary between the first divided exposure region and the second divided exposure region, wherein the one edge is defined, in part, through the use of a first cutout portion, formed in a first mask, that extends in a first direction past a stitching portion and into the second divided exposure region;

exposing the resist film in the second divided exposure region to form a latent image which defines another edge of the resist pattern, opposite the one edge, in the vicinity of the boundary, wherein the other edge is defined, in part, through the use of a second cutout portion, formed in a second mask, that extends in a second direction past the stitching portion and into the first divided exposure region, where the second direction is opposite of the first direction; and

developing the resist film to form the resist pattern.

2. A method of manufacturing a thin film transistor substrate, comprising the steps of forming a plurality of bus lines extending on a substrate with an insulation film interposed; and forming a plurality of thin film transistors connected to any of the plurality of bus lines, wherein the bus lines are formed using the pattern forming method according to claim 1 .

3. A method of manufacturing a thin film transistor substrate according to claim 2 , wherein the bus lines are storage capacitor bus lines.

4. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates, wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 3 .

5. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates,wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 2 .

6. A pattern forming method according to claim 1 , wherein said first mask includes a first projection and said second mask includes a second projection, and further wherein during the step of exposing the resist film in the second divided exposure region, the second projection of the second mask is aligned to generally correspond with a previous position of the first cutout portion of the first mask and the second cutout portion of the second mask is aligned to generally correspond with a previous position of the first projection of the first mask.

7. A pattern forming method for forming a wiring pattern on a substrate having a plurality of divided exposure regions, the wiring pattern extending across a first divided exposure region and a second divided exposure region adjacent to each other among the plurality of divided exposure regions, the method comprising the steps of:

forming a wiring layer for forming the wiring pattern on the substrate;

forming a resist film on the wiring layer;

exposing the resist film in the first divided exposure region using a first exposure mask to form a latent image which defines one edge of the wiring pattern in the vicinity of a boundary between the first divided exposure region and the second divided exposure region;

exposing the resist film in the second divided exposure region using a second exposure mask to form a latent image which defines another edge of the wiring pattern in the vicinity of the boundary;

developing the resist film to form the resist pattern;

etching the wiring layer using the resist pattern as an etching mask to form the wiring pattern; and

correcting a relative misalignment of the first and second exposure masks relative to the substrate based on a pattern width of the wiring pattern formed in the vicinity of the boundary.

8. A pattern forming method according to claim 7 , wherein the correction is made by measuring the pattern width of the wiring pattern and calculating the direction and amount of a misalignment of the first and second exposure masks relative to the substrate.

9. A method of manufacturing a thin film transistor substrate, comprising the steps of forming a plurality of bus lines extending on a substrate with an insulation film interposed; and forming a plurality of thin film transistors connected to any of the plurality of bus lines, wherein the bus lines are formed using the pattern forming method according to claim 8 .

10. A method of manufacturing a thin film transistor substrate according to claim 9 , wherein the bus lines are storage capacitor bus lines.

11. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates, wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 10 .

12. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates, wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 9 .

13. A method of manufacturing a thin film transistor substrate, comprising the steps of forming a plurality of bus lines extending on a substrate with an insulation film interposed; and forming a plurality of thin film transistors connected to any of the plurality of bus lines, wherein the bus lines are formed using the pattern forming method according to claim 7 .

14. A method of manufacturing a thin film transistor substrate according to claim 13 , wherein the bus lines are storage capacitor bus lines.

15. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates, wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 14 .

16. A method of manufacturing a liquid crystal display comprising a liquid crystal sealed between two substrates, wherein at least either of the two substrates is fabricated using the method of manufacturing a thin film transistor substrate according to claim 13 .

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2005
From: FUJITSU LIMITED
To: SHARP KABUSHIKI KAISHA
Reel/Frame 016345/0210 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2005
From: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
To: FUJITSU LIMITED
Reel/Frame 016345/0310 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2004
From: TAKIZAWA, HIDEAKI
To: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
Reel/Frame 015568/0842 →