Bitline booster circuit and method
View Patent ↗A circuit and method for boosting bitline performance uses a bitline booster circuit to allow long bitlines, with large numbers of memory cells attached, to discharge to a digital zero in a faster time. One bitline booster circuit requires only two additional NOR gates, two additional transistors, and one additional control signal. Consequently, the bitline booster circuit does not require a significant number of added components, does not require multiple control signals and takes up minimal additional silicon area.
1. The A boosted memory array comprising:
at least one bitline;
at least one memory cell coupled to said bitline;
a bitline booster circuit coupled to said bitline;
a bitline booster circuit bitline boost enable signal input terminal coupled to said bitline booster circuit;
a bitline boost enable signal coupled to said bitline booster circuit bitline boost enable signal input terminal, wherein;
when said bitline boost enable signal is active and a signal on said at least one bitline starts going low, said bitline booster circuit discharges said at least one bitline, further wherein;
said boosted memory array includes at least two bitlines, a first bitline and a second bitline, further wherein;
said bitline booster circuit comprises:
a first NOR gate, a first input of said first NOR gate being coupled to said first bitline and a second input of said first NOR gate being coupled to said bitline boost enable signal;
a first transistor, an output of said first NOR gate being coupled to a control electrode of said first transistor, a first flow electrode of said first transistor being coupled said first bitline, a second flow electrode of said first transistor being coupled to a supply voltage;
a second NOR gate, a second input of said second NOR gate being coupled to said second bitline and a second input of said second NOR gate being coupled to said bitline boost enable signal; and
a second transistor, an output of said second NOR gate being coupled to a control electrode of said second transistor, a first flow electrode of said second transistor being coupled said second bitline, a second flow electrode of said second transistor being coupled to said supply voltage.
2. The boosted memory array of claim 1 , wherein;
said first and second transistors are NFETS and said supply voltage is ground.
3. The boosted memory array of claim 1 , wherein;
said boosted memory array is on the same silicon chip as a microprocessor.
4. A microprocessor chip, said microprocessor chip comprising:
one or more functional blocks; and
a boosted memory array, said boosted memory array comprising:
at least one bitline;
at least one memory cell coupled to said bitline;
a bitline booster circuit coupled to said bitline;
a bitline booster circuit bitline boost enable signal input terminal coupled to said bitline booster circuit;
a bitline boost enable signal coupled to said bitline booster circuit bitline boost enable signal input terminal, wherein;
when said bitline boost enable signal is active and a signal on said at least one bitline starts going low, said bitline booster circuit discharges said at least one bitline, further wherein:
said boosted memory array includes at least two bitlines, a first bitline and a second bitline, further wherein;
said bitline boost enable signal is active only during write operation, further wherein;
said bitline booster circuit comprises:
a first NOR gate, a first input of said first NOR gate being coupled to said first bitline and a second input of said first NOR gate being coupled to said bitline boost enable signal;
a first transistor, an output of said first NOR gate being coupled to a control electrode of said first transistor, a first flow electrode of said first transistor being coupled said first bitline, a second flow electrode of said first transistor being coupled to a supply voltage;
a second NOR gate, a first input of said second NOR gate being coupled to said second bitline and a second input of said second NOR gate being coupled to said bitline boost enable signal; and
a second transistor, an output of said second NOR gate being coupled to a control electrode of said second transistor, a first flow electrode of said second transistor being coupled said second bitline, a second flow electrode of said second transistor being coupled to said supply voltage.
5. The microprocessor chip of claim 4 , wherein;
said first and second transistors are NFETS and said supply voltage is ground.
6. A method for boosting the performance of a memory array comprising:
providing at least one bitline;
coupling at least one memory cell to said at least one bitline;
coupling a bitline booster circuit to said at least one bitline;
coupling a bitline booster circuit bitline boost enable signal input terminal to said bitline booster circuit;
coupling a bitline boost enable signal to said bitline booster circuit bitline boost enable signal input terminal, such that;
when said bitline boost enable signal is active and a signal on said at least one bitline starts going low, said bitline booster circuit discharges said at least one bitline, wherein;
said boosted memory array includes at least two bitlines, a first bitline and a second bitline, further wherein;
said bitline boost enable signal is active only during write operation, further wherein;
said bitline booster circuit comprises:
a first NOR gate, a first input of said first NOR gate being coupled to said first bitline and a second input of said first NOR gate being coupled to said bitline boost enable signal;
a first transistor, an output of said first NOR gate being coupled to a control electrode of said first transistor, a first flow electrode of said first transistor being coupled said first bitline, a second flow electrode of said first transistor being coupled to a supply voltage;
a second NOR gate, a first input of said second NOR gate being coupled to said second bitline and a second input of said second NOR gate being coupled to said bitline boost enable signal; and
a second transistor, an output of said second NOR gate being coupled to a control electrode of said second transistor, a first flow electrode of said second transistor being coupled said second bitline, a second flow electrode of said second transistor being coupled to said supply voltage.
7. The method for boosting the performance of a memory array of claim 6 , wherein;
said first and second transistors are NFETS and said supply voltage is ground.
8. The method for boosting the performance of a memory array of claim 6 , wherein;
said boosted memory array is on the same silicon chip as a microprocessor.
9. A method for improving the performance of a microprocessor chip, said method comprising:
providing one or more functional blocks on said microprocessor chip;
providing a boosted memory array, said boosted memory array comprising:
at least one bitline;
at least one memory cell coupled to said bitline;
a bitline booster circuit coupled to said bitline;
a bitline booster circuit bitline boost enable signal input terminal coupled to said bitline booster circuit;
a bitline boost enable signal coupled to said bitline booster circuit bitline boost enable signal input terminal, wherein;
when said bitline boost enable signal is active and a signal on said at least one bitline starts going low, said bitline booster circuit discharges said at least one bitline, further wherein;
said bitline boost enable signal is active only during write operation, further wherein;
said bitline booster circuit comprises:
a first NOR gate, a first input of said first NOR gate being coupled to said first bitline and a second input of said first NOR gate being coupled to said bitline boost enable signal;
a first transistor, an output of said first NOR gate being coupled to a control electrode of said first transistor, a first flow electrode of said first transistor being coupled said first bitline, a second flow electrode of said first transistor being coupled to a supply voltage;
a second NOR gate, a first input of said second NOR gate being coupled to said second bitline and a second input of said second NOR gate being coupled to said bitline boost enable signal; and
a second transistor, an output of said second NOR gate being coupled to a control electrode of said second transistor, a first flow electrode of said second transistor being coupled said second bitline, a second flow electrode of said second transistor being coupled to said supply voltage.
10. The method for improving the performance of a microprocessor chip of claim 9 , wherein;
said first and second transistors are NFETS and said supply voltage is ground.