Method for transconductance linearization for DC-coupled applications
View Patent ↗A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the first transconductance stage becomes active before the second transconductance stage with respect to the magnitude of a differential input voltage, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current converter. As each of the plurality of transconductance stages is biased differently from the others, the various transconductance stages are biased on to differing amounts based upon the biasing signals as well as the input signal.
1. A class AB transconductance block, comprising:
a first transconductance stage comprising MOSFET amplification devices operably coupled to produce a first differential current from a differential input voltage based on a first bias voltage;
a second transconductance stage comprising MOSFET amplification devices operably coupled to produce a second differential current based on the differential input voltage and a second bias voltage;
a third transconductance stage comprising MOSFET amplification devices operably coupled to produce a third differential current based on the differential input voltage and a third bias voltage, wherein output current of the class AB transconductance block is a sum of the first differential current, the second differential current and the third differential current; and
a resistor ladder operable as a biasing circuit operably coupled to produce the first bias voltage, the second bias voltage and the third bias voltage, wherein the first bias voltage is greater than the second bias voltage and wherein the second bias voltage is greater than the third bias voltage and wherein each bias voltage for each of the transconductance stage is produced from an output end of a resistor of the resistor ladder.
2. The class AB transconductance block of claim 1 , wherein the first transconductance stage further comprises:
a first transistor operably coupled to receive a combination of a first leg of the differential input voltage and the first bias voltage; and
a second transistor operably coupled to receive a combination of a second leg of the differential input voltage and the first bias voltage, wherein the second transistor is operably coupled to the first transistor such that the first transistor produces a first leg of the first differential current and the second transistor produces a second leg of the first differential current.
3. The class AB transconductance block of claim 1 , wherein the second transconductance stage further comprises:
a first transistor operably coupled to receive a combination of a first leg of the differential input voltage and the secondary bias voltage; and
a second transistor operably coupled to receive a combination of a second leg of the differential input voltage and the secondary bias voltage, wherein the second transistor is operably coupled to the first transistor such that the first transistor produces a first leg of the secondary differential current and the second transistor produces a second leg of the secondary differential current.
4. The class AB transconductance block of claim 3 further including a third transconductance stage, the third transconductance stage further comprising:
a first transistor operably coupled to receive a combination of a first leg of the differential input voltage end the secondary bias voltage; and
a second transistor operably coupled to receive a combination of a second leg of the differential input voltage and the secondary bias voltage, wherein the second transistor is operably coupled to the first transistor such that the first transistor produces a first leg of the secondary differential current and the second transistor produces a second leg of the secondary differential current.
5. The class AB transconductance block of claim 4 further including a fourth transconductance stage, the fourth transconductance stage further comprising:
a first transistor operably coupled to receive a combination of a first leg of the differential input voltage and the secondary bias voltage; and
a second transistor operably coupled to receive a combination of a second leg of the differential input voltage and the secondary bias voltage, wherein the second transistor is operably coupled to the first transistor such that the first transistor produces a first leg of the secondary differential current end the second transistor produces a second leg of the secondary differential current.
6. The class AB transconductance block of claim 5 further including a fifth transconductance stage, the fifth transconductance stage further comprising:
a first transistor operably coupled to receive a combination of a first leg of the differential input voltage and the secondary bias voltage; and
a second transistor operably coupled to receive a combination of a second leg of the differential input voltage and the secondary bias voltage, wherein the second transistor is operably coupled to the first transistor such that the first transistor produces a first leg of the secondary differential current and the second transistor produces a second leg of the secondary differential current.
7. The class AB transconductance block of claim 1 , wherein the biasing circuit further comprises a reference current source operably coupled to a current mirror to produce a bias signal.
8. The class AB transconductance block of claim 1 , further including:
a biasing circuit, wherein the biasing circuit further comprises:
a first reference voltage source operably coupled to produce the first bias voltage;
a second reference voltage source operably coupled to produce the secondary bias voltage;
a first resistive pair operably coupled to provide the first bias voltage to the first transconductance stage; and
a second resistive pair operably coupled to provide the secondary bias voltage to the secondary transconductance stage.
9. The class AB transconductance block of claim 1 further comprises:
a fourth transconductance stage operably coupled to produce a fourth differential current based on the differential input voltage and a fourth bias voltage, wherein output current of the class AB voltage current converter is the sum of the first differential current, the secondary differential current, and the third differential current, and the fourth differential current wherein the biasing circuit produces the fourth bias voltage, wherein the third bias voltage is greater than the fourth bias voltage.
10. The class AB transconductance block of claim 9 further comprises:
a fifth transconductance stage operably coupled to produce a fifth differential current based on the differential input voltage and a fifth bias voltage, wherein output current of the class AB voltage current converter is the sum of the first differential current, the second differential current, the third differential current, the fourth differential current and the fifth differential current, wherein the biasing circuit produces the fifth bias voltage, wherein the fourth bias voltage is greater than the fifth bias voltage.
11. A class AB transconductance block, comprising:
a first transconductance stage operably coupled to produce a first differential current from a differential input voltage based on a first bias voltage;
a second transconductance stage operably coupled to produce a second differential current based on the differential input voltage and a second bias voltage, wherein output current of the class AB transconductance block is a sum of the first differential current and the secondary differential current;
a resistor ladder comprising a plurality of resistors wherein at least one resistor is coupled between each transconductance stage of the class AB transconductance block; and
wherein each transconductance stage is biased to a different voltage level relative to all other transconductance stages.
12. The class AB transconductance block of claim 11 further comprising a third transconductance stage.
13. The class AB transconductance block of claim 12 further comprising a fourth transconductance stage.
14. The class AB transconductance block of claim 13 further comprising at least five transconductance stages.