Display device including a plurality of cascade-connected driver ICs
View Patent ↗A display device disclosed herein prevents timing misalignment between signals of clock, data, and start pulses to be supplied to driver ICs. The display device comprises a controller, driver ICs and other components and each driver IC is configured to receive clock, data, and start pulses output from the controller, supply the received clock, data, and start pulses to a switch through parallel paths without routing the signals through its internal circuit, and supply the received clock, data, and start pulses to output terminals via the switch.
1. A display device comprising:
a controller which outputs start pulses, data, and a clock and a plurality of drivers which are cascade connected, each of said plurality of drivers comprising a start pulse input terminal for receiving said start pulses, a data input terminal for receiving said data, a clock input terminal for receiving said clock, a start pulse output terminal for outputting said start pulses received, a data output terminal for outputting said data received, a clock output terminal for outputting said clock received, and an internal circuit which captures said data that has been input in response to one of said start pulses in synchronization with said clock,
wherein each of said plurality of drivers further comprises a switch for transmitting signals to a following-stage cascade-connected driver and connects said start pulse input terminal to said start pulse output terminal, said data input terminal to said data output terminal, and said clock input terminal to said clock output terminal by a switch control signal.
2. The display device as recited in claim 1 , wherein, in response to a first supplied start pulse, said internal circuit outputs the switch control signal to turn on the switch which was being off not to transmit said first supplied start pulse to a next-stage driver.
3. A display device comprising:
a controller which outputs start pulses, data, and a clock and a plurality of drivers which are cascade connected, each of said plurality of drivers comprising a start pulse input terminal for receiving said start pulses, a data input terminal for receiving said data, a clock input terminal for receiving said clock, a start pulse output terminal for outputting said start pulses received, a data output terminal for outputting said data received, a clock output terminal for outputting said clock received, and an internal circuit which captures said data that has been input in response to one of said start pulses in synchronization with said clock,
wherein said start pulse input terminal is electrically connected to said start pulse output terminal by a path, said data input terminal is electrically connected to said data output terminal by a path, and said clock input terminal is electrically connected to said clock output terminal by a path, wherein these paths are not via said internal circuit, and
wherein each said driver further comprises a first phase aligning circuit connected to said start pulse input terminal, said clock input terminal, and said data input terminal, and said start pulses, said clock, and said data that have been input are phase aligned through said first phase aligning circuit and then supplied to said start pulse output terminal, said clock output terminal, and said data output terminal.
4. The display device as recited in claim 3 , wherein each said driver further comprises a second phase aligning circuit connected to said start pulse output terminal, said clock output terminal, and said data output terminal, and said start pulses, said clock, and said data passing through said first phase aligning circuit are phase aligned again and then supplied to said start pulse output terminal, said clock output terminal, and said data output terminal.
5. A display device comprising:
a controller which outputs start pulses, data, and a clock and a plurality of drivers which are cascade connected, each of said plurality of drivers comprising a start pulse input terminal for receiving said start pulses, a data input terminal for receiving said data, a clock input terminal for receiving said clock, a start pulse output terminal for outputting said start pulses received, a data output terminal for outputting said data received, a clock output terminal for outputting said clock received, and an internal circuit which captures said data that has been input in response to one of said start pulses in synchronization with said clock, wherein each said driver further comprises a setting register and setting data is captured through said data input terminal and written into said setting register, and
wherein each said driver further comprises a self recognizing circuit and said self recognizing circuit outputs a setting data control signal at timing when a start pulse has changed to a predetermined value and permits writing of said setting data supplied from said data input terminal into said setting register.
6. A display device comprising:
a controller which outputs start pulses, data, and a clock and a plurality of drivers which are cascade connected, each of said plurality of drivers comprising a start pulse input terminal for receiving said start pulses, a data input terminal for receiving said data, a clock input terminal for receiving said clock, a start pulse output terminal for outputting said start pulses received, a data output terminal for outputting said data received, a clock output terminal for outputting said clock received, and an internal circuit which captures said data that has been input in response to one of said start pulses in synchronization with said clock, and
wherein each said driver further comprises a first self recognizing circuit for capturing pixel data output from said controller and a second self recognizing circuit for capturing setting data output from said controller.
7. The display device as recited in claim 6 , wherein said first self recognizing circuit permits capturing of said pixel data transmitted on a data line into the internal circuit at timing when the number of said start pulses has reached a first value and said second self recognizing circuit permits writing of said setting data transmitted on said data line into the setting register at timing when the number of said start pulses has reached a second value.
8. The display device as recited in claim 6 , wherein each said driver further comprises a first phase aligning circuit connected to said start pulse input terminal, said clock input terminal, and said data input terminal, and said start pulses, said clock, and said data that have been input are phase aligned through said first phase aligning circuit and then supplied to said start pulse output terminal, said clock output terminal, and said data output terminal.
9. The display device as recited in claim 8 , wherein each said driver further comprises a second phase aligning circuit connected to said start pulse output terminal, said clock output terminal, and said data output terminal, and said start pulses, said clock, and said data passing through said first phase aligning circuit are phase aligned again and then supplied to said start pulse output terminal, said clock output terminal, and said data output terminal.