IP Library Granted Patent US 6,967,513
Granted Patent B1
US 6,967,513 · App. 10/770,064 · Granted Nov 22, 2005

Phase-locked loop filter with out of band rejection in low bandwidth mode

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Quick Facts
Patent No.
US 6,967,513
App. No.
10/770,064
Granted
Nov 22, 2005
Kind
B1
Abstract

A wideband impedance attenuator includes a phase-locked loop filter, a voltage-controlled oscillator connected to the phase-locked loop filter during transmit, and an impedance circuit connected to the phase-locked loop filter and the voltage controlled oscillator. The impedance circuit is a scaled version of the phase-locked loop filter. Moreover, the wideband impedance attenuator attenuates a Gaussian frequency shift key modulation signal by a factor of 1/(N+1) using the impedance circuit, which has an impedance of N*Z(s), and the phase-locked loop filter, which has an impedance of Z(s). An output frequency is generated using a voltage-controlled oscillator wherein the output frequency corresponds to the attenuated Gaussian frequency shift key modulation signal. In addition, a comparator compares a voltage of an output from the programmable gain amplifier with a voltage necessary to produce a predetermined frequency shift in a voltage-controlled oscillator to produce a gain signal. A gain controller, in response to the gain signal produced by the comparator, controls a gain of the programmable gain amplifier.

Claims (37)

1. A phase-locked loop filter, comprising:

an integration circuit;

a phase lead-lag frequency compensation circuit;

a capacitor;

a charging circuit to pre-charge said capacitor to a voltage of said phase-locked loop filter; and

a switch to switch said capacitor into the phase-locked loop filter.

2. The phase-locked loop filter as claimed in claim 1 , further comprising:

a second capacitor; and

a second switch to switch said second capacitor into the phase-locked loop filter;

said charging circuit pre-charging said second capacitor to a voltage of said phase-locked loop filter.

3. The phase-locked loop filter as claimed in claim 2 , further comprising:

a third capacitor; and

a third switch to switch said second capacitor into the phase-locked loop filter;

said charging circuit pre-charging said third capacitor to a voltage of said phase-locked loop filter.

4. The phase-locked loop filter as claimed in claim 1 , further comprising:

a filter pole circuit to roll-off a response above a phase-locked loop cutoff.

5. The phase-locked loop filter as claimed in claim 1 , further comprising:

a first integration resistor/capacitor pair to extend a response of the phase-locked loop filter.

6. The phase-locked loop filter as claimed in claim 5 , further comprising:

a second integration resistor/capacitor pair to further extend the response of the phase-locked loop filter.

7. The phase-locked loop filter as claimed in claim 1 , further comprising:

a predetermined number of integration resistor/capacitor pairs to extend a response of the phase-locked loop filter.

8. A method for phase-locked loop filtering an output from a programmable charge pump, comprising:

(a) integrating the output of the programmable charge pump;

(b) phase lead-lag frequency compensating the output of the programmable charge pump;

(c) pre-charging a capacitor to a voltage of a phase-locked loop filter; and

(d) switching the capacitor into a the phase-locked loop filter.

9. The method as claimed in claim 8 , further comprising:

(e) rolling-off a response above a phase-locked loop cutoff.

10. A phase-locked loop filter, comprising:

an integration capacitor;

a series combination of a lead resistor and a lag capacitor connected in parallel to said integration capacitor; and

a series combination of a second lead resistor and a second lag capacitor connected in parallel to said lag capacitor.

11. The phase-locked loop filter as claimed in claim 10 , further comprising:

a series combination of a third lead resistor and a third lag capacitor connected in parallel to said second lag capacitor.

12. The phase-locked loop filter as claimed in claim 11 , further comprising:

a series combination of a fourth lead resistor and a fourth lag capacitor connected in parallel to said third lag capacitor.