Configurable electronic device with mixed granularity

1. A configurable electronic device comprising:

at least one configurable basic assembly comprising

a programmable circuit comprising a plurality of programmable elements and a first configurable interconnection network for mutually connecting said plurality of programmable circuits,

a second configurable interconnection network,

a plurality of configurable arithmetic cells mutually connected by said second configurable interconnection network;

a third configurable interconnection network linking said programmable circuit and said plurality of configurable arithmetic cells, and

a control bus between said programmable circuit and said plurality of configurable arithmetic cells, and also extending within said plurality of configurable arithmetic cells,

said programmable circuit generating clock and control signals for said plurality of arithmetic cells.

2. A configurable electronic device according to claim 1 , wherein each configurable arithmetic cell comprises at least one arithmetic and logic unit (ALU), an address generator, and a memory connected to said control bus.

3. A configurable electronic device according to claim 1 , wherein said programmable circuit has a programming granularity of less than or equal to 4 bits.

4. A configurable electronic device according to claim 1 , wherein said plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one row of cells.

5. A configurable electronic device according to claim 1 , wherein said plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one column of cells.

6. A configurable electronic device according claim 2 , wherein said second configurable interconnection network for each arithmetic cell comprises:

a first data bus defining a horizontal bus connecting said memory and said at least one ALU, said first data bus also connecting at least one of said third interconnection network and said first data bus in another arithmetic cell of a same row; and

a second data bus defining a vertical bus connecting said memory and said at least one ALU, said second data bus also connecting to a vertical bus of another arithmetic cell of a same column.

7. A configurable electronic device according to claim 1 , wherein said at least one configurable basic assembly comprises a plurality of mutually connected configurable basic assemblies.

8. A configurable electronic device according to claim 1 , wherein said programmable circuit comprising a field programmable gate array.

9. A configurable electronic device according to claim 1 , further comprising a substrate with said at least one configurable basic assembly thereon so that the configurable electronic device comprises an integrated circuit.

10. An electronic device comprising:

a plurality of configurable basic assemblies connected together, each configurable basic assembly comprising

a programmable circuit comprising a plurality of programmable elements and a first configurable interconnection network for mutually connecting said plurality of programmable circuits,

a second configurable interconnection network,

a plurality of configurable arithmetic cells mutually connected by said second configurable interconnection network, each configurable arithmetic cell comprising at least one arithmetic and logic unit (ALU), an address generator, and a memory;

a third configurable interconnection network linking said programmable circuit and said plurality of configurable arithmetic cells, and

a control bus between said programmable circuit and said plurality of configurable arithmetic cells,

and also extending within said plurality of configurable arithmetic cells.

11. An electronic device according to claim 10 , wherein each configurable arithmetic cell comprises at least one arithmetic and logic unit (ALU), an address generator, and a memory connected to said control bus.

12. An electronic device according to claim 10 , wherein each programmable circuit generates clock and control signals for said plurality of arithmetic cells associated therewith.

13. An electronic device according to claim 10 , wherein said programmable circuit has a programming granularity of less than or equal to 4 bits.

14. An electronic device according to claim 10 , wherein said plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one row of cells.

15. An electronic device according to claim 10 , wherein said plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one column of cells.

16. An electronic device according claim 11 , wherein said second configurable interconnection network for each arithmetic cell comprises:

a first data bus defining a horizontal bus connecting said memory and said at least one ALU, said first data bus also connecting at least one of said third interconnection network and said first data bus in another arithmetic cell of a same row; and

a second data bus defining a vertical bus connecting said memory and said at least one ALU, said second data bus also connecting to a vertical bus of another arithmetic cell of a same column.

17. An electronic device according to claim 10 , wherein said programmable circuit comprising a field programmable gate array.

18. A method for making a configurable electronic device comprising:

providing at least one configurable basic assembly comprising

mutually connecting a plurality of programmable elements using a first configurable interconnection network for defining a programmable circuit,

mutually connecting a plurality of configurable arithmetic cells using a second configurable interconnection network;

connecting the programmable circuit and the plurality of configurable arithmetic cells using a third configurable interconnection network, and

connecting a control bus between the programmable circuit and the plurality of configurable arithmetic cells, the control bus also extending within the plurality of configurable arithmetic cells.

19. A method according to claim 18 , wherein each configurable arithmetic cell comprises at least one arithmetic and logic unit (ALU), an address generator, and a memory connected to the control bus.

20. A method according to claim 18 , wherein the programmable circuit generates clock and control signals for the plurality of arithmetic cells.

21. A method according to claim 18 , wherein the programmable circuit has a programming granularity of less than or equal to 4 bits.

22. A method according to claim 18 , wherein the plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one row of cells.

23. A method according to claim 18 , wherein the plurality of arithmetic cells include at least two arithmetic cells mutually connected to form at least one column of cells.

24. A method according claim 19 , wherein the second configurable interconnection network for each arithmetic cell comprises:

a first data bus defining a horizontal bus connecting the memory and the at least one ALU, the first data bus also connecting at least one of the third interconnection network and the first data bus in another arithmetic cell of a same row; and

a second data bus defining a vertical bus connecting the memory and the at least one ALU, the second data bus also connecting to a vertical bus of another arithmetic cell of a same column.

25. A method according to claim 18 , wherein the at least one configurable basic assembly comprises a plurality of mutually connected configurable basic assemblies.

26. A method according to claim 18 , wherein the programmable circuit comprising a field programmable gate array.