Granted Patent B2

US 7,002,404 · App. 10/773,710 · Granted Feb 21, 2006

Abstract

Claims (30)

1. Tuning circuit for tuning a filter stage, wherein the filter stage comprises:

(a) at least one RC element with an RC time constant, with the RC time constant being the product of the resistance of a resistor and the capacitance of a capacitor which is connected at a potential node to the resistor; and

(b) an operational amplifier including a first signal input which is connected to the potential node and including a signal output which is fed back via the capacitor to the first signal input of the operational amplifier;

wherein the tuning circuit comprises:

(c) a comparator including a first input which is connected to the signal output of the operational amplifier and including a second input which is alternatively connectable to a first reference voltage source which generates a first reference voltage, or to a second reference voltage source which generates a second reference voltage; and

(d) a controller which is connected to the comparator, the controller including a sequence controller,

wherein the capacitor has its charge varied by means of switches which are controlled by the sequence controller, until the first reference voltage is applied to the first input of the comparator, and the capacitor then has its charge varied in the opposite direction by means of switches which are controlled by the sequence controller until the second reference voltage is applied to the first input of the comparator,

wherein a digital counter contained in the sequence controller records a charge variation time for varying the charge of the capacitor;

(e) wherein the controller switches a capacitor array as a function of the recorded charge variation time, and

wherein the capacitor array is connected in parallel with the capacitor of the RC element in order to compensate for any discrepancy between the RC time constant of the RC element and a nominal value of the RC time constant.

2. Tuning circuit according to claim 1 , wherein the filter stage is contained in an integrated analog filter.

3. Tuning circuit according to claim 1 , wherein the switches are CMOS switches.

4. Tuning circuit according to claim 1 , wherein the digital counter of the sequence controller is clocked by means of an external clock signal.

5. Tuning circuit according to claim 1 , wherein the digital counter for the sequence controller counts a number of clock cycles from the external clock signal between reception of a start signal and reception of a stop signal which is received from the comparator.

6. Tuning circuit according to claim 1 , wherein the controller has a memory which is connected to the sequence controller.

7. Tuning circuit according to claim 6 , wherein a coded tuning control signal for switching the capacitor array is stored in the memory for each count of the digital counter.

8. Tuning circuit according to claim 7 , wherein the capacitor array has two or more tuning capacitors which are connected in parallel with the capacitor in the RC element as a function of the coded tuning control signal.

9. Tuning circuit according to claim 1 , wherein the capacitor array is integrated in the filter stage.

10. Tuning circuit according to claim 2 , wherein the integrated analog filter is switchable between a normal filter mode and a tuning mode by means of switches which are controlled by the sequence controller.

11. Tuning circuit according to claim 2 , wherein the analog filter is an anti-aliasing filter.

12. Tuning circuit according to claim 11 , wherein the analog filter is an xDSL anti-aliasing filter.

13. Tuning circuit according to claim 2 , wherein the analog filter is a biquad filter.

14. Tuning circuit according to claim 2 , wherein the analog filter is a differential analog filter.

15. Tuning circuit according to claim 2 , wherein the analog filter has two or more filter stages.

16. Method for tuning a filter stage, the filter stage includes an RC element with an RC time constant, wherein the RC time constant is the product of the resistance of a resistor in the RC element and the capacitance of a capacitor in the RC element, the capacitor is connected in series with the resistor of the RC element, the method comprising:

(a) varying the charge on the capacitor by at least one RC element in the filter stage;

(b) measuring the charge variation time until the voltage which is produced at the potential node between the resistor and the capacitor in the RC element reaches a reference voltage;

(c) switching a capacitor array, which is connected in parallel with the capacitor in the RC element, as a function of the measured charge variation time, in order to compensate for any discrepancy between the RC time constant of the RC element and a predetermined nominal value of the RC time constant; and

(d) charging the capacitor in the element to a specific first reference voltage before the tuning of the filter stage;

(e) wherein, in order to tune the filter stage, varying the charge on the capacitor until the voltage which is dropped across the capacitor is equal to a second reference voltage, and it is then charged in the opposite direction until the voltage which is dropped across the capacitor is once again equal to the first reference voltage.

Assignments (9)