Method for fabricating semiconductor integrated circuit device
View Patent ↗A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
1. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an isolation groove between a plurality of active regions in a first major surface of a wafer;
(b) forming an insulating region in the isolation groove by depositing an insulating layer;
(c) synthesizing water vapor from oxygen and hydrogen gases by use of a catalyst;
(d) keeping the thus synthesized water vapor in a gaseous state and feeding it into a processing chamber to form a wet oxidative atmosphere;
(e) after step (b), performing thermal oxidation treatment to a silicon surface portion over one of the active regions to form an insulating film under the wet oxidative atmosphere in the processing chamber.
2. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein said wet oxidative atmosphere includes oxygen gas as a principal oxidative gas component.
3. A method for fabricating a semiconductor integrated circuit device according to claim 2 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
4. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein said wet oxidative atmosphere includes oxygen gas as a principal gas component.
5. A method for fabricating a semiconductor integrated circuit device according to claim 4 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
6. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
7. A method for fabricating a semiconductor integrated circuit device according to claim 6 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
8. A method for fabricating a semiconductor integrated circuit device according to claim 7 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
9. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (e).
10. A method for fabricating a semiconductor integrated circuit device according to claim 9 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
11. A method for fabricating a semiconductor integrated circuit device according to claim 9 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
12. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein the planarization is performed by a chemical mechanical method.
13. A method for fabricating a semiconductor integrated circuit device according to claim 12 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
14. A method for fabricating a semiconductor integrated circuit device according to claim 12 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
15. A method for fabricating a semiconductor integrated circuit device according to claim 12 , wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (e).
16. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein the planarization is performed by a chemical mechanical polishing.
17. A method for fabricating a semiconductor integrated circuit device according to claim 16 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
18. A method for fabricating a semiconductor integrated circuit device according to claim 16 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
19. A method for fabricating a semiconductor integrated circuit device according to claim 16 , wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (e).
20. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein the deposition of the insulating layer is performed by chemical vapor deposition.
21. A method for fabricating a semiconductor integrated circuit device acctording to claim 20 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
22. A method for fabricating a semiconductor integrated circuit device according to claim 20 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
23. A method for fabricating a semiconductor integrated circuit device according to claim 20 , wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (e).
24. A method for fabricating a semiconductor integrated circuit device according to claim 20 , wherein the planarization is performed by a chemical mechanical method.
25. A method for fabricating a semiconductor integrated circuit device according to claim 20 , wherein the planarization is performed by chemical mechanical polishing.
26. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein a temperature of the thermal oxidation is not lower than 800° C.
27. A method for fabricating a semiconductor integrated circuit device according to claim 1 , wherein the thermal oxidation is performed while feeding said oxidative atmosphere over the first major surface of said wafer.
28. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein the gate insulating film is a gate insulating film of an insulated gate field effect transistor.
29. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein the gate length of said insulated gate field effect transistor is not more than 0.25 μm.
30. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein planarization is performed by removing the insulating layer outside the isolation groove between steps (b) and (e).
31. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein the planarization is performed by a chemical mechanical method.
32. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein the planarization is performed by chemical mechanical polishing.
33. A method for fabricating a semiconductor integrated circuit device according to claim 27 , wherein the deposition of the insulating layer is performed by chemical vapor deposition.