Semiconductor, memory card, and data processing system
View Patent ↗Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.
1. A command format for a nonvolatile memory, comprising:
a first command format;
a second command format; and
a third command format,
wherein said first command format comprises a first type command, and address information after said first type command,
wherein said second command format comprises said first type command, said address information, and a second type command, said address information being located between said first type command and said second type command,
wherein said third command format comprises said first type command, said address information, data and said second type command, said address information being located between said first type command and said second type command, and said data being located between said address information and said second type command,
wherein said first type command indicates an arbitrary one of operations, and
wherein all of said first type command, said second type command, said address information and said data are received into an input/output terminal of said nonvolatile memory.
2. A nonvolatile memory comprising:
a plurality of input/output terminals; and
a control circuit,
wherein said control circuit is capable of receiving an arbitrary one of a plurality of commands via said plurality of input/output terminals,
wherein said plurality of commands comprise a first type format command, a second type format command, and a third type format command,
wherein said first type format command includes a first type command without a second type command, and address information after said first type command,
wherein said second type format command includes said first type command, said second type command after said first type command, and said address information located between said first type command and said second type command,
wherein said third type format command includes said first type command, said second type command after said first type command, said address information located between said first type command and said second type command, and data located between said address information and said second type command,
wherein said first type command indicates an arbitrary one of operations, and
wherein said second type command indicates a termination of each of said second type format command and said third type format command.
3. A nonvolatile memory according to claim 2 ,
wherein said first type format command includes a first read command, a first write command and an erase command, and
wherein said second type format command includes a second write command.
4. A nonvolatile memory according to claim 3 , further comprising a nonvolatile memory array and a latch circuit.
5. A nonvolatile memory according to claim 4 ,
wherein said control circuit controls outputting data read out from said nonvolatile memory array according to said address information when receiving said first read command.
6. A nonvolatile memory according to claim 4
wherein said control circuit controls writing data stored in said latch circuit to said nonvolatile memory array according to said address information when receiving said first write command.
7. A nonvolatile memory according to claim 4
wherein said control circuit controls erasing data stored in said nonvolatile memory array according to said address information when receiving said erase command.
8. A nonvolatile memory according to claim 4
wherein said control circuit controls writing data received from outside to said nonvolatile memory array according to said address information when receiving said second write command.