Reduced-size integrated phase-locked loop
View Patent ↗A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.
1. A phase-locked loop comprising:
a comparator generating a control voltage depending on the phase-shift between a predetermined reference signal and a feedback signal;
an oscillator controlled by the control voltage, generating a plurality of phase-shifted signals of same period, one of the phase-shifted signals forming the output signal of the phase-locked loop;
a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal; and
control means controlling the multiplexer to successively provide predetermined fractions of some of the phase-shifted signals, so that the divider, having a fixed predetermined dividing ratio (N), receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.
2. The phase-locked loop of claim 1 wherein the voltage-controlled oscillator generates a number n of phase-shifted signals of same period Tout so that the phase-shifted signal forming the output signal of the loop is ahead of each of the other phase-shifted signals by a duration equal to an integral multiple of a duration Tout/n, each of the phase-shifted signals consisting in a periodic pulse having a duration shorter than duration Tout/n.
3. The phase-locked loop of claim 2 wherein the control means is a sigma/delta modulator controlling the multiplexer so that the divider receives a signal, the average period (Tint) of which is equal to the sum of duration Tout/n multiplied by a first programmable Integer M ranging between 0 and n−1 and of duration Tout/n multiplied by a second programmable integer x coded over a number u of bits and divided by 2 u .
4. The phase-locked loop of claim 1 wherein the period of the signals generated by the oscillator depends on the control voltage.
5. The phase-locked loop of claim 1 wherein the comparator comprises:
a phase detector receiving as an input the reference signal and the feedback signal;
a change pump coupled to the output of the phase detector, generating a current signal depending on the phase difference between the reference and feedback signals; and
a filter generating the control voltage based on the current signal.