CMOS imaging system with low fixed pattern noise
View Patent ↗A CMOS imager system including an active pixel sensor having an access supply which provides distributed feedback, a column buffer (having gain and FPN suppression), and an A/D converter co-located with the sensor such that the effective transmission path between the column buffer (or optional analog PGA) and the A/D converter acts as a resistor, rather than a reactance. The system may further include both an analog gain amplifier stage and a digital programmable amplifier stage.
1. A CMOS imager system comprising:
an active pixel sensor;
a column buffer connected to the active pixel sensor;
an analog-to-digital (A/D) converter co-located with the active pixel sensor and column buffer; and
an analog programmable gain amplifier connected between the column buffer and the A/D converter, such that a transmission path between the analog programmable gain amplifier and the A/D converter acts primarily as a resistance, rather than a reactance.
2. The CMOS imager system of claim 1 , wherein the active pixel sensor comprises an access supply, a tapered reset supply and a source supply.
3. The CMOS imager system of claim 2 , wherein the A/D converter is a high-speed converter have 12 bit or greater resolution.
4. The CMOS imager system of claim 3 , wherein the column buffer has gain and fixed-pattern noise (FPN) suppression.
5. The CMOS imager system of claim 4 , wherein the analog programmable gain amplifier has tunable electronic bandwidth.
6. A digital video system comprising:
an active pixel sensor;
a column buffer connected to receive an output from the active pixel sensor;
an analog programmable gain amplifier connected to the column buffer;
an analog-to-digital (A/D) converter connected to the analog programmable gain amplifier and co-located with the active pixel sensor, column buffer and analog programmable gain amplifier, such that a transmission path between the analog gain amplifier and the A/D converter acts primarily as a resistance, rather than a reactance;
a digital programmable gain amplifier connected to an output of the A/D converter; and
a digital video interface connected to an output of the digital programmable gain amplifier.
7. The digital video system of claim 6 , wherein the active pixel sensor comprises an access supply, a tapered reset supply and a source supply.
8. The digital video system of claim 7 , wherein the A/D converter is a high-s.
9. The digital video system of claim 8 , wherein the column buffer has gain and fixed-pattern noise (FPN) suppression.
10. The digital video system of claim 9 , wherein the analog programmable gain amplifier has tunable electronic bandwidth.
11. A CMOS imager system comprising:
an active pixel sensor;
a column buffer connected to the active pixel sensor;
a high-speed analog-to-digital (A/D) converter, the A/D converter having greater than or equal to 12 bit resolution, co-located with the active pixel sensor and supporting multiple column buffers; and
an analog programmable gain amplifier connected between the column buffer and the A/D converter, such that a transmission path between the analog programmable gain amplifier and the A/D converter acts primarily as a resistance, rather than a reactance.
12. The CMOS imager system of claim 11 , wherein the active pixel sensor comprises an access supply, a tapered reset supply and a source supply.
13. The CMOS imager system of claim 12 , wherein the column buffer has gain and fixed-pattern noise (FPN) suppression.
14. The CMOS imager system of claim 13 , wherein the analog programmable gain amplifier has tunable electronic bandwidth.