Method of manufacturing semiconductor device having damascene interconnection
View Patent ↗In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1 . In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm 2 .
1. A method of manufacturing a semiconductor device comprising a process for forming a seed layer in a via hole or a wiring-trench formed in an interlayer insulating film formed on a semiconductor substrate, and then burying a wiring material using an electroplating method, wherein said electroplating method includes a current step for flowing a current in the direction opposite to the direction for growing the plating so as to cancel a concentration gradient of a brightener which accelerates the growth of plating.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein said current step comprises three steps: a first step for flowing a current only in the direction for growing the plating; a second step for flowing a current only in the direction opposite to the direction for growing the plating; and a third current step for flowing only in the direction identical to said first step; in the order of said first, second, and third steps.
3. The method of manufacturing a semiconductor device according to claim 1 , wherein said step flowing a current only in the direction opposite to the direction for growing the plating is configured so that the absolute value of the product of the current and the time is within a range between 1.0 and 120 mA×sec/cm2.
4. The method of manufacturing a semiconductor device according to claim 2 , wherein said second current step is configured so that the absolute value of the product of the current and the time is within a range between 1.0 and 120 mA×sec/cm2.
5. The method of manufacturing a semiconductor device according to claim 2 , wherein said first current step is configured so that the product of the current and the time is within a range between 120 and 2700 mA×sec/cm2.
6. The method of manufacturing a semiconductor device according to claim 4 , wherein said first current step is configured so that the product of the current and the time is within a range between 120 and 2700 mA×sec/cm2.
7. The method of manufacturing a semiconductor device according to claim 2 , wherein the current value of said first current step is within a range between 0.5 and 13 mA/cm2.
8. The method of manufacturing a semiconductor device according to claim 4 , wherein the current value of said first current step is within a range between 0.5 and 13 mA/cm2.
9. The method of manufacturing a semiconductor device according to claim 2 , wherein the current value of said third current step is within a range between 16 and 90 mA/cm2.
10. The method of manufacturing a semiconductor device according to claim 4 , wherein the current value of said third current step is within a range between 16 and 90 mA/cm2.
11. The method of manufacturing a semiconductor device according to claim 6 , wherein the current value of said third current step is within a range between 16 and 90 mA/cm2.
12. The method of manufacturing a semiconductor device according to claim 1 , wherein said wiring material is copper.